2006-08-30 05:12:40 +07:00
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/*
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* pata_sl82c105.c - SL82C105 PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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2011-10-13 18:16:24 +07:00
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* (C) 2011 Bartlomiej Zolnierkiewicz
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2006-08-30 05:12:40 +07:00
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*
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* Based in part on linux/drivers/ide/pci/sl82c105.c
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* SL82C105/Winbond 553 IDE driver
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*
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* and in part on the documentation and errata sheet
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2007-02-21 00:51:51 +07:00
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*
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*
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* Note: The controller like many controllers has shared timings for
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* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
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* in the dma_stop function. Thus we actually don't need a set_dmamode
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* method as the PIO method is always called and will set the right PIO
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* timing parameters.
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2006-08-30 05:12:40 +07:00
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_sl82c105"
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2008-01-28 23:08:23 +07:00
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#define DRV_VERSION "0.3.3"
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2006-08-30 05:12:40 +07:00
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enum {
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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CTRL_IDE_IRQB = (1 << 30),
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CTRL_IDE_IRQA = (1 << 28),
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CTRL_LEGIRQ = (1 << 11),
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CTRL_P1F16 = (1 << 5),
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CTRL_P1EN = (1 << 4),
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CTRL_P0F16 = (1 << 1),
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CTRL_P0EN = (1 << 0)
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};
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/**
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* sl82c105_pre_reset - probe begin
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2007-08-06 16:36:23 +07:00
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* @link: ATA link
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 14:50:52 +07:00
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* @deadline: deadline jiffies for the operation
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2006-08-30 05:12:40 +07:00
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*
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* Set up cable type and use generic probe init
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*/
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2006-08-31 11:03:49 +07:00
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2007-08-06 16:36:23 +07:00
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static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
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2006-08-30 05:12:40 +07:00
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{
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static const struct pci_bits sl82c105_enable_bits[] = {
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{ 0x40, 1, 0x01, 0x01 },
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{ 0x40, 1, 0x10, 0x10 }
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};
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2007-08-06 16:36:23 +07:00
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struct ata_port *ap = link->ap;
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2006-08-30 05:12:40 +07:00
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2006-09-26 23:53:38 +07:00
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if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
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return -ENOENT;
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2008-04-07 20:47:16 +07:00
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return ata_sff_prereset(link, deadline);
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2006-08-30 05:12:40 +07:00
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}
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/**
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* sl82c105_configure_piomode - set chip PIO timing
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static u16 pio_timing[5] = {
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0x50D, 0x407, 0x304, 0x242, 0x240
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};
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u16 dummy;
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int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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pci_write_config_word(pdev, timing, pio_timing[pio]);
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/* Can we lose this oddity of the old driver */
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pci_read_config_word(pdev, timing, &dummy);
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}
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/**
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* sl82c105_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* sl82c105_configure_dmamode - set DMA mode in chip
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static u16 dma_timing[3] = {
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0x707, 0x201, 0x200
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};
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u16 dummy;
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int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
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int dma = adev->dma_mode - XFER_MW_DMA_0;
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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pci_write_config_word(pdev, timing, dma_timing[dma]);
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/* Can we lose this oddity of the old driver */
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pci_read_config_word(pdev, timing, &dummy);
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}
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/**
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* sl82c105_reset_engine - Reset the DMA engine
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* @ap: ATA interface
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*
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* The sl82c105 has some serious problems with the DMA engine
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2006-08-31 11:03:49 +07:00
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* when transfers don't run as expected or ATAPI is used. The
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2006-08-30 05:12:40 +07:00
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* recommended fix is to reset the engine each use using a chip
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* test register.
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_reset_engine(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 val;
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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pci_read_config_word(pdev, 0x7E, &val);
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pci_write_config_word(pdev, 0x7E, val | 4);
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pci_write_config_word(pdev, 0x7E, val & ~4);
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}
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/**
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* sl82c105_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* Reset the DMA engine each use as recommended by the errata
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2006-08-31 11:03:49 +07:00
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* document.
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2006-08-30 05:12:40 +07:00
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*
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* FIXME: if we switch clock at BMDMA start/end we might get better
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* PIO performance on DMA capable devices.
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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2007-02-11 03:36:14 +07:00
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udelay(100);
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2006-08-30 05:12:40 +07:00
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sl82c105_reset_engine(ap);
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2007-02-11 03:36:14 +07:00
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udelay(100);
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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/* Set the clocks for DMA */
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sl82c105_configure_dmamode(ap, qc->dev);
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2006-08-31 11:03:49 +07:00
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/* Activate DMA */
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2006-08-30 05:12:40 +07:00
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ata_bmdma_start(qc);
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}
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/**
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* sl82c105_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* Reset the DMA engine each use as recommended by the errata
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* document.
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*
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* This function is also called to turn off DMA when a timeout occurs
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* during DMA operation. In both cases we need to reset the engine,
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* so no actual eng_timeout handler is required.
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*
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* We assume bmdma_stop is always called if bmdma_start as called. If
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* not then we may need to wrap qc_issue.
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*/
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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ata_bmdma_stop(qc);
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sl82c105_reset_engine(ap);
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2007-02-11 03:36:14 +07:00
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udelay(100);
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2006-08-31 11:03:49 +07:00
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2006-08-30 05:12:40 +07:00
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/* This will redo the initial setup of the DMA device to matching
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PIO timings */
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2007-02-21 00:51:51 +07:00
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sl82c105_set_piomode(ap, qc->dev);
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2006-08-30 05:12:40 +07:00
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}
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2008-01-28 23:08:23 +07:00
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/**
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* sl82c105_qc_defer - implement serialization
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* @qc: command
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*
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* We must issue one command per host not per channel because
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* of the reset bug.
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*
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* Q: is the scsi host lock sufficient ?
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*/
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static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
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{
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struct ata_host *host = qc->ap->host;
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struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
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int rc;
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2008-05-20 04:56:10 +07:00
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/* First apply the usual rules */
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2008-01-28 23:08:23 +07:00
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rc = ata_std_qc_defer(qc);
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if (rc != 0)
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return rc;
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/* Now apply serialization rules. Only allow a command if the
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other channel state machine is idle */
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if (alt && alt->qc_active)
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return ATA_DEFER_PORT;
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return 0;
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}
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2010-10-08 22:02:13 +07:00
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static bool sl82c105_sff_irq_check(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
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pci_read_config_dword(pdev, 0x40, &val);
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return val & mask;
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}
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2006-08-30 05:12:40 +07:00
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static struct scsi_host_template sl82c105_sht = {
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2008-03-25 10:22:49 +07:00
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ATA_BMDMA_SHT(DRV_NAME),
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2006-08-30 05:12:40 +07:00
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};
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static struct ata_port_operations sl82c105_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
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.inherits = &ata_bmdma_port_ops,
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.qc_defer = sl82c105_qc_defer,
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2006-08-30 05:12:40 +07:00
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.bmdma_start = sl82c105_bmdma_start,
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.bmdma_stop = sl82c105_bmdma_stop,
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
|
|
|
.cable_detect = ata_cable_40wire,
|
|
|
|
.set_piomode = sl82c105_set_piomode,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:50 +07:00
|
|
|
.prereset = sl82c105_pre_reset,
|
2010-10-08 22:02:13 +07:00
|
|
|
.sff_irq_check = sl82c105_sff_irq_check,
|
2006-08-31 11:03:49 +07:00
|
|
|
};
|
2006-08-30 05:12:40 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* sl82c105_bridge_revision - find bridge version
|
|
|
|
* @pdev: PCI device for the ATA function
|
|
|
|
*
|
|
|
|
* Locates the PCI bridge associated with the ATA function and
|
|
|
|
* providing it is a Winbond 553 reports the revision. If it cannot
|
|
|
|
* find a revision or the right device it returns -1
|
|
|
|
*/
|
2006-08-31 11:03:49 +07:00
|
|
|
|
2006-08-30 05:12:40 +07:00
|
|
|
static int sl82c105_bridge_revision(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *bridge;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The bridge should be part of the same device, but function 0.
|
|
|
|
*/
|
|
|
|
bridge = pci_get_slot(pdev->bus,
|
|
|
|
PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
|
|
|
|
if (!bridge)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure it is a Winbond 553 and is an ISA bridge.
|
|
|
|
*/
|
|
|
|
if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
|
|
|
|
bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
|
|
|
|
bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
|
|
|
|
pci_dev_put(bridge);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* We need to find function 0's revision, not function 1
|
|
|
|
*/
|
|
|
|
pci_dev_put(bridge);
|
2007-06-09 05:46:36 +07:00
|
|
|
return bridge->revision;
|
2006-08-30 05:12:40 +07:00
|
|
|
}
|
|
|
|
|
2011-10-13 18:16:24 +07:00
|
|
|
static void sl82c105_fixup(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, 0x40, &val);
|
|
|
|
val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
|
|
|
|
pci_write_config_dword(pdev, 0x40, val);
|
|
|
|
}
|
2006-08-31 11:03:49 +07:00
|
|
|
|
2006-08-30 05:12:40 +07:00
|
|
|
static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
2007-05-04 17:43:58 +07:00
|
|
|
static const struct ata_port_info info_dma = {
|
2007-05-28 17:59:48 +07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2006-08-30 05:12:40 +07:00
|
|
|
.port_ops = &sl82c105_port_ops
|
|
|
|
};
|
2007-05-04 17:43:58 +07:00
|
|
|
static const struct ata_port_info info_early = {
|
2007-05-28 17:59:48 +07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2006-08-30 05:12:40 +07:00
|
|
|
.port_ops = &sl82c105_port_ops
|
|
|
|
};
|
2007-05-04 17:43:58 +07:00
|
|
|
/* for now use only the first port */
|
|
|
|
const struct ata_port_info *ppi[] = { &info_early,
|
2008-01-28 23:08:23 +07:00
|
|
|
NULL };
|
2006-08-30 05:12:40 +07:00
|
|
|
int rev;
|
2008-03-25 10:22:47 +07:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = pcim_enable_device(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-08-30 05:12:40 +07:00
|
|
|
|
|
|
|
rev = sl82c105_bridge_revision(dev);
|
2006-08-31 11:03:49 +07:00
|
|
|
|
2006-08-30 05:12:40 +07:00
|
|
|
if (rev == -1)
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_warn(&dev->dev,
|
|
|
|
"pata_sl82c105: Unable to find bridge, disabling DMA\n");
|
2006-08-30 05:12:40 +07:00
|
|
|
else if (rev <= 5)
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_warn(&dev->dev,
|
|
|
|
"pata_sl82c105: Early bridge revision, no DMA available\n");
|
2007-05-04 17:43:58 +07:00
|
|
|
else
|
|
|
|
ppi[0] = &info_dma;
|
2006-08-31 11:03:49 +07:00
|
|
|
|
2011-10-13 18:16:24 +07:00
|
|
|
sl82c105_fixup(dev);
|
2006-08-30 05:12:40 +07:00
|
|
|
|
2010-05-20 03:10:22 +07:00
|
|
|
return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
|
2006-08-30 05:12:40 +07:00
|
|
|
}
|
|
|
|
|
2011-10-13 18:16:24 +07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int sl82c105_reinit_one(struct pci_dev *pdev)
|
|
|
|
{
|
2013-06-03 12:05:36 +07:00
|
|
|
struct ata_host *host = pci_get_drvdata(pdev);
|
2011-10-13 18:16:24 +07:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
sl82c105_fixup(pdev);
|
|
|
|
|
|
|
|
ata_host_resume(host);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-09-29 07:21:59 +07:00
|
|
|
static const struct pci_device_id sl82c105[] = {
|
|
|
|
{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
|
|
|
|
|
|
|
|
{ },
|
2006-08-30 05:12:40 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver sl82c105_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = sl82c105,
|
|
|
|
.probe = sl82c105_init_one,
|
2011-10-13 18:16:24 +07:00
|
|
|
.remove = ata_pci_remove_one,
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = sl82c105_reinit_one,
|
|
|
|
#endif
|
2006-08-30 05:12:40 +07:00
|
|
|
};
|
|
|
|
|
2012-04-19 12:43:05 +07:00
|
|
|
module_pci_driver(sl82c105_pci_driver);
|
2006-08-30 05:12:40 +07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for Sl82c105");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, sl82c105);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|