2013-07-18 15:52:33 +07:00
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/*
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* TI clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/ti.h>
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#include <linux/of.h>
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2013-10-22 15:39:36 +07:00
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#include <linux/of_address.h>
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#include <linux/list.h>
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2013-07-18 15:52:33 +07:00
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2014-12-16 23:20:46 +07:00
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#include "clock.h"
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2013-07-18 15:52:33 +07:00
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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2013-10-22 15:39:36 +07:00
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struct ti_clk_ll_ops *ti_clk_ll_ops;
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2014-09-12 19:01:57 +07:00
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static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
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2013-10-22 15:39:36 +07:00
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2013-07-18 15:52:33 +07:00
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/**
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* ti_dt_clocks_register - register DT alias clocks during boot
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* @oclks: list of clocks to register
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*
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* Register alias or non-standard DT clock entries during boot. By
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* default, DT clocks are found based on their node name. If any
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* additional con-id / dev-id -> clock mapping is required, use this
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* function to list these.
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*/
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void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
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{
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struct ti_dt_clk *c;
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struct device_node *node;
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struct clk *clk;
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struct of_phandle_args clkspec;
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for (c = oclks; c->node_name != NULL; c++) {
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node = of_find_node_by_name(NULL, c->node_name);
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clkspec.np = node;
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clk = of_clk_get_from_provider(&clkspec);
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if (!IS_ERR(clk)) {
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c->lk.clk = clk;
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clkdev_add(&c->lk);
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} else {
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pr_warn("failed to lookup clock node %s\n",
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c->node_name);
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}
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}
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}
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2013-10-22 15:39:36 +07:00
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struct clk_init_item {
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struct device_node *node;
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struct clk_hw *hw;
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ti_of_clk_init_cb_t func;
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struct list_head link;
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};
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static LIST_HEAD(retry_list);
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/**
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* ti_clk_retry_init - retries a failed clock init at later phase
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* @node: device not for the clock
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* @hw: partially initialized clk_hw struct for the clock
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* @func: init function to be called for the clock
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*
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* Adds a failed clock init to the retry list. The retry list is parsed
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* once all the other clocks have been initialized.
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*/
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int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
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ti_of_clk_init_cb_t func)
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{
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struct clk_init_item *retry;
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pr_debug("%s: adding to retry list...\n", node->name);
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retry = kzalloc(sizeof(*retry), GFP_KERNEL);
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if (!retry)
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return -ENOMEM;
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retry->node = node;
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retry->func = func;
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retry->hw = hw;
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list_add(&retry->link, &retry_list);
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return 0;
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}
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/**
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* ti_clk_get_reg_addr - get register address for a clock register
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* @node: device node for the clock
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* @index: register index from the clock node
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*
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* Builds clock register address from device tree information. This
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* is a struct of type clk_omap_reg.
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*/
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void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
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{
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struct clk_omap_reg *reg;
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u32 val;
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u32 tmp;
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2014-09-12 19:01:57 +07:00
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int i;
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2013-10-22 15:39:36 +07:00
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reg = (struct clk_omap_reg *)&tmp;
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2014-09-12 19:01:57 +07:00
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for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
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if (clocks_node_ptr[i] == node->parent)
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break;
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}
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if (i == CLK_MAX_MEMMAPS) {
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pr_err("clk-provider not found for %s!\n", node->name);
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return NULL;
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}
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reg->index = i;
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2013-10-22 15:39:36 +07:00
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if (of_property_read_u32_index(node, "reg", index, &val)) {
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pr_err("%s must have reg[%d]!\n", node->name, index);
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return NULL;
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}
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reg->offset = val;
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return (void __iomem *)tmp;
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}
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/**
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* ti_dt_clk_init_provider - init master clock provider
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* @parent: master node
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* @index: internal index for clk_reg_ops
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*
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2014-09-12 19:01:57 +07:00
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* Initializes a master clock IP block. This basically sets up the
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* mapping from clocks node to the memory map index. All the clocks
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* are then initialized through the common of_clk_init call, and the
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* clocks will access their memory maps based on the node layout.
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2013-10-22 15:39:36 +07:00
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*/
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void ti_dt_clk_init_provider(struct device_node *parent, int index)
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{
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struct device_node *clocks;
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/* get clocks for this parent */
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clocks = of_get_child_by_name(parent, "clocks");
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if (!clocks) {
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pr_err("%s missing 'clocks' child node.\n", parent->name);
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return;
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}
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2014-09-12 19:01:57 +07:00
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/* add clocks node info */
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clocks_node_ptr[index] = clocks;
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}
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2013-10-22 15:39:36 +07:00
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2014-09-12 19:01:57 +07:00
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/**
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* ti_dt_clk_init_retry_clks - init clocks from the retry list
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*
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* Initializes any clocks that have failed to initialize before,
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* reasons being missing parent node(s) during earlier init. This
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* typically happens only for DPLLs which need to have both of their
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* parent clocks ready during init.
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*/
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void ti_dt_clk_init_retry_clks(void)
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{
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struct clk_init_item *retry;
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struct clk_init_item *tmp;
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int retries = 5;
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while (!list_empty(&retry_list) && retries) {
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list_for_each_entry_safe(retry, tmp, &retry_list, link) {
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pr_debug("retry-init: %s\n", retry->node->name);
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retry->func(retry->hw, retry->node);
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list_del(&retry->link);
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kfree(retry);
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}
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retries--;
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2013-10-22 15:39:36 +07:00
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}
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}
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2014-12-16 23:20:46 +07:00
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2015-02-03 23:59:32 +07:00
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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2014-12-16 23:20:46 +07:00
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void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
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{
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while (*patch) {
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memcpy((*patch)->patch, *patch, sizeof(**patch));
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patch++;
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}
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}
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struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
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{
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struct clk *clk;
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struct ti_clk_fixed *fixed;
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struct ti_clk_fixed_factor *fixed_factor;
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struct clk_hw *clk_hw;
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if (setup->clk)
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return setup->clk;
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switch (setup->type) {
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case TI_CLK_FIXED:
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fixed = setup->data;
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clk = clk_register_fixed_rate(NULL, setup->name, NULL,
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CLK_IS_ROOT, fixed->frequency);
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break;
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2014-12-16 23:20:47 +07:00
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case TI_CLK_MUX:
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clk = ti_clk_register_mux(setup);
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break;
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2014-12-16 23:20:50 +07:00
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case TI_CLK_DIVIDER:
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clk = ti_clk_register_divider(setup);
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break;
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2014-12-16 23:20:52 +07:00
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case TI_CLK_COMPOSITE:
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clk = ti_clk_register_composite(setup);
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break;
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2014-12-16 23:20:46 +07:00
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case TI_CLK_FIXED_FACTOR:
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fixed_factor = setup->data;
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clk = clk_register_fixed_factor(NULL, setup->name,
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fixed_factor->parent,
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0, fixed_factor->mult,
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fixed_factor->div);
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break;
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2014-12-16 23:20:48 +07:00
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case TI_CLK_GATE:
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clk = ti_clk_register_gate(setup);
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break;
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2015-01-30 03:24:28 +07:00
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case TI_CLK_DPLL:
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clk = ti_clk_register_dpll(setup);
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break;
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2014-12-16 23:20:46 +07:00
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default:
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pr_err("bad type for %s!\n", setup->name);
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clk = ERR_PTR(-EINVAL);
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}
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if (!IS_ERR(clk)) {
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setup->clk = clk;
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if (setup->clkdm_name) {
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if (__clk_get_flags(clk) & CLK_IS_BASIC) {
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pr_warn("can't setup clkdm for basic clk %s\n",
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setup->name);
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} else {
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clk_hw = __clk_get_hw(clk);
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to_clk_hw_omap(clk_hw)->clkdm_name =
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setup->clkdm_name;
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omap2_init_clk_clkdm(clk_hw);
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}
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}
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}
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return clk;
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}
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int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
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{
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struct clk *clk;
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bool retry;
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struct ti_clk_alias *retry_clk;
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struct ti_clk_alias *tmp;
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while (clks->clk) {
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clk = ti_clk_register_clk(clks->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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list_add(&clks->link, &retry_list);
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} else {
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pr_err("register for %s failed: %ld\n",
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clks->clk->name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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} else {
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clks->lk.clk = clk;
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clkdev_add(&clks->lk);
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}
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clks++;
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}
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retry = true;
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while (!list_empty(&retry_list) && retry) {
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retry = false;
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list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
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pr_debug("retry-init: %s\n", retry_clk->clk->name);
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clk = ti_clk_register_clk(retry_clk->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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continue;
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} else {
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pr_err("register for %s failed: %ld\n",
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retry_clk->clk->name,
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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} else {
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retry = true;
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retry_clk->lk.clk = clk;
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clkdev_add(&retry_clk->lk);
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list_del(&retry_clk->link);
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}
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}
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}
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return 0;
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}
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2015-02-03 23:59:32 +07:00
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#endif
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