2009-07-21 16:23:57 +07:00
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/*
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* Copyright 2009 VMware, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Michel Dänzer
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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2012-06-05 05:45:15 +07:00
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#define RADEON_TEST_COPY_BLIT 1
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#define RADEON_TEST_COPY_DMA 0
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2009-07-21 16:23:57 +07:00
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/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
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2012-06-05 05:45:15 +07:00
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static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
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2009-07-21 16:23:57 +07:00
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{
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2009-11-20 20:29:23 +07:00
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struct radeon_bo *vram_obj = NULL;
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struct radeon_bo **gtt_obj = NULL;
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2009-07-21 16:23:57 +07:00
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uint64_t gtt_addr, vram_addr;
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2013-07-01 23:39:34 +07:00
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unsigned n, size;
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int i, r, ring;
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2012-06-05 05:45:15 +07:00
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switch (flag) {
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case RADEON_TEST_COPY_DMA:
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ring = radeon_copy_dma_ring_index(rdev);
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break;
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case RADEON_TEST_COPY_BLIT:
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ring = radeon_copy_blit_ring_index(rdev);
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break;
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default:
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DRM_ERROR("Unknown copy method\n");
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return;
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}
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2009-07-21 16:23:57 +07:00
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size = 1024 * 1024;
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/* Number of tests =
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2011-08-19 22:24:16 +07:00
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* (Total GTT - IB pool - writeback page - ring buffers) / test size
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2009-07-21 16:23:57 +07:00
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*/
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2014-07-17 23:20:32 +07:00
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n = rdev->mc.gtt_size - rdev->gart_pin_size;
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2011-08-19 22:24:16 +07:00
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n /= size;
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2009-07-21 16:23:57 +07:00
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gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
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if (!gtt_obj) {
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DRM_ERROR("Failed to allocate %d pointers\n", n);
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r = 1;
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goto out_cleanup;
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}
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2011-02-18 23:59:16 +07:00
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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2014-09-18 19:11:56 +07:00
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0, NULL, NULL, &vram_obj);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to create VRAM object\n");
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goto out_cleanup;
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}
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_reserve(vram_obj, false);
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if (unlikely(r != 0))
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2013-06-27 18:48:26 +07:00
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goto out_unref;
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to pin VRAM object\n");
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2013-06-27 18:48:26 +07:00
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goto out_unres;
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2009-07-21 16:23:57 +07:00
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}
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for (i = 0; i < n; i++) {
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void *gtt_map, *vram_map;
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void **gtt_start, **gtt_end;
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void **vram_start, **vram_end;
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2013-06-27 18:48:26 +07:00
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struct radeon_fence *fence = NULL;
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2009-07-21 16:23:57 +07:00
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2011-02-18 23:59:16 +07:00
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r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
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2014-09-18 19:11:56 +07:00
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RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
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gtt_obj + i);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to create GTT object %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean;
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2009-07-21 16:23:57 +07:00
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}
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_reserve(gtt_obj[i], false);
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if (unlikely(r != 0))
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unref;
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to pin GTT object %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unres;
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2009-07-21 16:23:57 +07:00
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}
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_kmap(gtt_obj[i], >t_map);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to map GTT object %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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for (gtt_start = gtt_map, gtt_end = gtt_map + size;
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gtt_start < gtt_end;
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gtt_start++)
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*gtt_start = gtt_start;
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2009-11-20 20:29:23 +07:00
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radeon_bo_kunmap(gtt_obj[i]);
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2009-07-21 16:23:57 +07:00
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2012-06-05 05:45:15 +07:00
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if (ring == R600_RING_TYPE_DMA_INDEX)
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2014-09-05 01:01:53 +07:00
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fence = radeon_copy_dma(rdev, gtt_addr, vram_addr,
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size / RADEON_GPU_PAGE_SIZE,
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2015-01-30 12:38:44 +07:00
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vram_obj->tbo.resv);
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2012-06-05 05:45:15 +07:00
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else
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2014-09-05 01:01:53 +07:00
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fence = radeon_copy_blit(rdev, gtt_addr, vram_addr,
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size / RADEON_GPU_PAGE_SIZE,
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2015-01-30 12:38:44 +07:00
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vram_obj->tbo.resv);
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2014-09-05 01:01:53 +07:00
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if (IS_ERR(fence)) {
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2009-07-21 16:23:57 +07:00
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DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
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2014-09-05 01:01:53 +07:00
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r = PTR_ERR(fence);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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r = radeon_fence_wait(fence, false);
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if (r) {
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DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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radeon_fence_unref(&fence);
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_kmap(vram_obj, &vram_map);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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for (gtt_start = gtt_map, gtt_end = gtt_map + size,
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vram_start = vram_map, vram_end = vram_map + size;
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vram_start < vram_end;
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gtt_start++, vram_start++) {
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if (*vram_start != gtt_start) {
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DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
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2011-08-19 22:24:17 +07:00
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"expected 0x%p (GTT/VRAM offset "
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"0x%16llx/0x%16llx)\n",
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i, *vram_start, gtt_start,
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(unsigned long long)
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(gtt_addr - rdev->mc.gtt_start +
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(void*)gtt_start - gtt_map),
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(unsigned long long)
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(vram_addr - rdev->mc.vram_start +
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(void*)gtt_start - gtt_map));
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2009-11-20 20:29:23 +07:00
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radeon_bo_kunmap(vram_obj);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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*vram_start = vram_start;
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}
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2009-11-20 20:29:23 +07:00
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radeon_bo_kunmap(vram_obj);
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2009-07-21 16:23:57 +07:00
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2012-06-05 05:45:15 +07:00
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if (ring == R600_RING_TYPE_DMA_INDEX)
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2014-09-05 01:01:53 +07:00
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fence = radeon_copy_dma(rdev, vram_addr, gtt_addr,
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size / RADEON_GPU_PAGE_SIZE,
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2015-01-30 12:38:44 +07:00
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vram_obj->tbo.resv);
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2012-06-05 05:45:15 +07:00
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else
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2014-09-05 01:01:53 +07:00
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fence = radeon_copy_blit(rdev, vram_addr, gtt_addr,
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size / RADEON_GPU_PAGE_SIZE,
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2015-01-30 12:38:44 +07:00
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vram_obj->tbo.resv);
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2014-09-05 01:01:53 +07:00
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if (IS_ERR(fence)) {
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2009-07-21 16:23:57 +07:00
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DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
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2014-09-05 01:01:53 +07:00
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r = PTR_ERR(fence);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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r = radeon_fence_wait(fence, false);
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if (r) {
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DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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radeon_fence_unref(&fence);
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2009-11-20 20:29:23 +07:00
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r = radeon_bo_kmap(gtt_obj[i], >t_map);
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2009-07-21 16:23:57 +07:00
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if (r) {
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DRM_ERROR("Failed to map GTT object after copy %d\n", i);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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for (gtt_start = gtt_map, gtt_end = gtt_map + size,
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vram_start = vram_map, vram_end = vram_map + size;
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gtt_start < gtt_end;
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gtt_start++, vram_start++) {
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if (*gtt_start != vram_start) {
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DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
|
2011-08-19 22:24:17 +07:00
|
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"expected 0x%p (VRAM/GTT offset "
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"0x%16llx/0x%16llx)\n",
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i, *gtt_start, vram_start,
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(unsigned long long)
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(vram_addr - rdev->mc.vram_start +
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(void*)vram_start - vram_map),
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(unsigned long long)
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(gtt_addr - rdev->mc.gtt_start +
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(void*)vram_start - vram_map));
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2009-11-20 20:29:23 +07:00
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radeon_bo_kunmap(gtt_obj[i]);
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2013-06-27 18:48:26 +07:00
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goto out_lclean_unpin;
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2009-07-21 16:23:57 +07:00
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}
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}
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2009-11-20 20:29:23 +07:00
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radeon_bo_kunmap(gtt_obj[i]);
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2009-07-21 16:23:57 +07:00
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DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18 04:54:29 +07:00
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gtt_addr - rdev->mc.gtt_start);
|
2013-06-27 18:48:26 +07:00
|
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continue;
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out_lclean_unpin:
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radeon_bo_unpin(gtt_obj[i]);
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out_lclean_unres:
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radeon_bo_unreserve(gtt_obj[i]);
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out_lclean_unref:
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radeon_bo_unref(>t_obj[i]);
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out_lclean:
|
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for (--i; i >= 0; --i) {
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radeon_bo_unpin(gtt_obj[i]);
|
|
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radeon_bo_unreserve(gtt_obj[i]);
|
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|
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radeon_bo_unref(>t_obj[i]);
|
|
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}
|
2014-09-05 01:01:53 +07:00
|
|
|
if (fence && !IS_ERR(fence))
|
2013-06-27 18:48:26 +07:00
|
|
|
radeon_fence_unref(&fence);
|
|
|
|
break;
|
2009-07-21 16:23:57 +07:00
|
|
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}
|
|
|
|
|
2013-06-27 18:48:26 +07:00
|
|
|
radeon_bo_unpin(vram_obj);
|
|
|
|
out_unres:
|
|
|
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radeon_bo_unreserve(vram_obj);
|
|
|
|
out_unref:
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|
|
|
radeon_bo_unref(&vram_obj);
|
2009-07-21 16:23:57 +07:00
|
|
|
out_cleanup:
|
2013-06-27 18:48:26 +07:00
|
|
|
kfree(gtt_obj);
|
2009-07-21 16:23:57 +07:00
|
|
|
if (r) {
|
2017-02-28 19:55:52 +07:00
|
|
|
pr_warn("Error while testing BO move\n");
|
2009-07-21 16:23:57 +07:00
|
|
|
}
|
|
|
|
}
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2012-06-05 05:45:15 +07:00
|
|
|
void radeon_test_moves(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
if (rdev->asic->copy.dma)
|
|
|
|
radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
|
|
|
|
if (rdev->asic->copy.blit)
|
|
|
|
radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
|
|
|
|
}
|
|
|
|
|
2013-04-08 17:41:29 +07:00
|
|
|
static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
|
|
|
|
struct radeon_ring *ring,
|
|
|
|
struct radeon_fence **fence)
|
|
|
|
{
|
2013-05-23 17:10:04 +07:00
|
|
|
uint32_t handle = ring->idx ^ 0xdeafbeef;
|
2013-04-08 17:41:29 +07:00
|
|
|
int r;
|
|
|
|
|
|
|
|
if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
|
2013-05-23 17:10:04 +07:00
|
|
|
r = radeon_uvd_get_create_msg(rdev, ring->idx, handle, NULL);
|
2013-04-08 17:41:29 +07:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to get dummy create msg\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2013-05-23 17:10:04 +07:00
|
|
|
r = radeon_uvd_get_destroy_msg(rdev, ring->idx, handle, fence);
|
2013-04-08 17:41:29 +07:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to get dummy destroy msg\n");
|
|
|
|
return r;
|
|
|
|
}
|
2013-05-23 17:10:04 +07:00
|
|
|
|
|
|
|
} else if (ring->idx == TN_RING_TYPE_VCE1_INDEX ||
|
|
|
|
ring->idx == TN_RING_TYPE_VCE2_INDEX) {
|
|
|
|
r = radeon_vce_get_create_msg(rdev, ring->idx, handle, NULL);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to get dummy create msg\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_vce_get_destroy_msg(rdev, ring->idx, handle, fence);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to get dummy destroy msg\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2013-04-08 17:41:29 +07:00
|
|
|
} else {
|
|
|
|
r = radeon_ring_lock(rdev, ring, 64);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
|
|
|
|
return r;
|
|
|
|
}
|
2017-04-24 15:45:51 +07:00
|
|
|
r = radeon_fence_emit(rdev, fence, ring->idx);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to emit fence\n");
|
|
|
|
radeon_ring_unlock_undo(rdev, ring);
|
|
|
|
return r;
|
|
|
|
}
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ring, false);
|
2013-04-08 17:41:29 +07:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-27 17:31:00 +07:00
|
|
|
void radeon_test_ring_sync(struct radeon_device *rdev,
|
2011-10-23 17:56:27 +07:00
|
|
|
struct radeon_ring *ringA,
|
|
|
|
struct radeon_ring *ringB)
|
2011-09-27 17:31:00 +07:00
|
|
|
{
|
2011-11-17 21:22:44 +07:00
|
|
|
struct radeon_fence *fence1 = NULL, *fence2 = NULL;
|
2011-09-27 17:31:00 +07:00
|
|
|
struct radeon_semaphore *semaphore = NULL;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = radeon_semaphore_create(rdev, &semaphore);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to create semaphore\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
2011-10-23 17:56:27 +07:00
|
|
|
r = radeon_ring_lock(rdev, ringA, 64);
|
2011-09-27 17:31:00 +07:00
|
|
|
if (r) {
|
2012-07-18 01:02:30 +07:00
|
|
|
DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
|
2011-09-27 17:31:00 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringA, false);
|
2013-04-08 17:41:29 +07:00
|
|
|
|
|
|
|
r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
|
|
|
|
if (r)
|
2012-05-08 19:24:01 +07:00
|
|
|
goto out_cleanup;
|
2013-04-08 17:41:29 +07:00
|
|
|
|
|
|
|
r = radeon_ring_lock(rdev, ringA, 64);
|
2012-05-08 19:24:01 +07:00
|
|
|
if (r) {
|
2013-04-08 17:41:29 +07:00
|
|
|
DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
|
2012-05-08 19:24:01 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2013-04-08 17:41:29 +07:00
|
|
|
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringA, false);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2013-04-08 17:41:29 +07:00
|
|
|
r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
|
|
|
|
if (r)
|
|
|
|
goto out_cleanup;
|
|
|
|
|
2011-09-27 17:31:00 +07:00
|
|
|
mdelay(1000);
|
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
if (radeon_fence_signaled(fence1)) {
|
|
|
|
DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
|
2011-09-27 17:31:00 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
2011-10-23 17:56:27 +07:00
|
|
|
r = radeon_ring_lock(rdev, ringB, 64);
|
2011-09-27 17:31:00 +07:00
|
|
|
if (r) {
|
2011-10-23 17:56:27 +07:00
|
|
|
DRM_ERROR("Failed to lock ring B %p\n", ringB);
|
2011-09-27 17:31:00 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringB, false);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
r = radeon_fence_wait(fence1, false);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to wait for sync fence 1\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
mdelay(1000);
|
|
|
|
|
|
|
|
if (radeon_fence_signaled(fence2)) {
|
|
|
|
DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_ring_lock(rdev, ringB, 64);
|
2011-09-27 17:31:00 +07:00
|
|
|
if (r) {
|
2011-11-17 21:22:44 +07:00
|
|
|
DRM_ERROR("Failed to lock ring B %p\n", ringB);
|
2011-09-27 17:31:00 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringB, false);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
r = radeon_fence_wait(fence2, false);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to wait for sync fence 1\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2011-09-27 17:31:00 +07:00
|
|
|
|
|
|
|
out_cleanup:
|
2012-05-10 21:46:43 +07:00
|
|
|
radeon_semaphore_free(rdev, &semaphore, NULL);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
if (fence1)
|
|
|
|
radeon_fence_unref(&fence1);
|
|
|
|
|
|
|
|
if (fence2)
|
|
|
|
radeon_fence_unref(&fence2);
|
|
|
|
|
|
|
|
if (r)
|
2017-02-28 19:55:52 +07:00
|
|
|
pr_warn("Error while testing ring sync (%d)\n", r);
|
2011-11-17 21:22:44 +07:00
|
|
|
}
|
|
|
|
|
2012-09-01 00:43:50 +07:00
|
|
|
static void radeon_test_ring_sync2(struct radeon_device *rdev,
|
2011-11-17 21:22:44 +07:00
|
|
|
struct radeon_ring *ringA,
|
|
|
|
struct radeon_ring *ringB,
|
|
|
|
struct radeon_ring *ringC)
|
|
|
|
{
|
|
|
|
struct radeon_fence *fenceA = NULL, *fenceB = NULL;
|
|
|
|
struct radeon_semaphore *semaphore = NULL;
|
|
|
|
bool sigA, sigB;
|
|
|
|
int i, r;
|
|
|
|
|
|
|
|
r = radeon_semaphore_create(rdev, &semaphore);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to create semaphore\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_ring_lock(rdev, ringA, 64);
|
|
|
|
if (r) {
|
2012-07-18 01:02:30 +07:00
|
|
|
DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
|
2011-11-17 21:22:44 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringA, false);
|
2011-11-17 21:22:44 +07:00
|
|
|
|
2013-04-08 17:41:29 +07:00
|
|
|
r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
|
|
|
|
if (r)
|
|
|
|
goto out_cleanup;
|
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
r = radeon_ring_lock(rdev, ringB, 64);
|
|
|
|
if (r) {
|
2012-07-18 01:02:30 +07:00
|
|
|
DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
|
2011-11-17 21:22:44 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringB, false);
|
2013-04-08 17:41:29 +07:00
|
|
|
r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
|
|
|
|
if (r)
|
|
|
|
goto out_cleanup;
|
2011-11-17 21:22:44 +07:00
|
|
|
|
|
|
|
mdelay(1000);
|
|
|
|
|
|
|
|
if (radeon_fence_signaled(fenceA)) {
|
|
|
|
DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
if (radeon_fence_signaled(fenceB)) {
|
2013-04-08 17:41:29 +07:00
|
|
|
DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
|
2011-11-17 21:22:44 +07:00
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_ring_lock(rdev, ringC, 64);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to lock ring B %p\n", ringC);
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringC, false);
|
2011-11-17 21:22:44 +07:00
|
|
|
|
|
|
|
for (i = 0; i < 30; ++i) {
|
|
|
|
mdelay(100);
|
|
|
|
sigA = radeon_fence_signaled(fenceA);
|
|
|
|
sigB = radeon_fence_signaled(fenceB);
|
|
|
|
if (sigA || sigB)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!sigA && !sigB) {
|
|
|
|
DRM_ERROR("Neither fence A nor B has been signaled\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
} else if (sigA && sigB) {
|
|
|
|
DRM_ERROR("Both fence A and B has been signaled\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
|
|
|
|
|
|
|
|
r = radeon_ring_lock(rdev, ringC, 64);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to lock ring B %p\n", ringC);
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-07-18 01:02:30 +07:00
|
|
|
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
|
2014-08-18 15:34:55 +07:00
|
|
|
radeon_ring_unlock_commit(rdev, ringC, false);
|
2011-11-17 21:22:44 +07:00
|
|
|
|
|
|
|
mdelay(1000);
|
|
|
|
|
|
|
|
r = radeon_fence_wait(fenceA, false);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to wait for sync fence A\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
r = radeon_fence_wait(fenceB, false);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to wait for sync fence B\n");
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
out_cleanup:
|
2012-05-10 21:46:43 +07:00
|
|
|
radeon_semaphore_free(rdev, &semaphore, NULL);
|
2011-11-17 21:22:44 +07:00
|
|
|
|
|
|
|
if (fenceA)
|
|
|
|
radeon_fence_unref(&fenceA);
|
|
|
|
|
|
|
|
if (fenceB)
|
|
|
|
radeon_fence_unref(&fenceB);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
|
|
|
if (r)
|
2017-02-28 19:55:52 +07:00
|
|
|
pr_warn("Error while testing ring sync (%d)\n", r);
|
2011-09-27 17:31:00 +07:00
|
|
|
}
|
|
|
|
|
2013-05-23 17:10:04 +07:00
|
|
|
static bool radeon_test_sync_possible(struct radeon_ring *ringA,
|
|
|
|
struct radeon_ring *ringB)
|
|
|
|
{
|
|
|
|
if (ringA->idx == TN_RING_TYPE_VCE2_INDEX &&
|
|
|
|
ringB->idx == TN_RING_TYPE_VCE1_INDEX)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2011-09-27 17:31:00 +07:00
|
|
|
void radeon_test_syncing(struct radeon_device *rdev)
|
|
|
|
{
|
2011-11-17 21:22:44 +07:00
|
|
|
int i, j, k;
|
2011-09-27 17:31:00 +07:00
|
|
|
|
|
|
|
for (i = 1; i < RADEON_NUM_RINGS; ++i) {
|
2011-10-23 17:56:27 +07:00
|
|
|
struct radeon_ring *ringA = &rdev->ring[i];
|
|
|
|
if (!ringA->ready)
|
2011-09-27 17:31:00 +07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
for (j = 0; j < i; ++j) {
|
2011-10-23 17:56:27 +07:00
|
|
|
struct radeon_ring *ringB = &rdev->ring[j];
|
|
|
|
if (!ringB->ready)
|
2011-09-27 17:31:00 +07:00
|
|
|
continue;
|
|
|
|
|
2013-05-23 17:10:04 +07:00
|
|
|
if (!radeon_test_sync_possible(ringA, ringB))
|
|
|
|
continue;
|
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
|
2011-10-23 17:56:27 +07:00
|
|
|
radeon_test_ring_sync(rdev, ringA, ringB);
|
2011-09-27 17:31:00 +07:00
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
|
2011-10-23 17:56:27 +07:00
|
|
|
radeon_test_ring_sync(rdev, ringB, ringA);
|
2011-11-17 21:22:44 +07:00
|
|
|
|
|
|
|
for (k = 0; k < j; ++k) {
|
|
|
|
struct radeon_ring *ringC = &rdev->ring[k];
|
2012-01-05 17:02:42 +07:00
|
|
|
if (!ringC->ready)
|
|
|
|
continue;
|
2011-11-17 21:22:44 +07:00
|
|
|
|
2013-05-23 17:10:04 +07:00
|
|
|
if (!radeon_test_sync_possible(ringA, ringC))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!radeon_test_sync_possible(ringB, ringC))
|
|
|
|
continue;
|
|
|
|
|
2011-11-17 21:22:44 +07:00
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
|
|
|
|
radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
|
|
|
|
|
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
|
|
|
|
radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
|
|
|
|
|
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
|
|
|
|
radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
|
|
|
|
|
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
|
|
|
|
radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
|
|
|
|
|
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
|
|
|
|
radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
|
|
|
|
|
|
|
|
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
|
|
|
|
radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
|
|
|
|
}
|
2011-09-27 17:31:00 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|