2017-05-26 18:13:25 +07:00
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/*
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* Copyright © 2016-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "i915_drv.h"
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#include "intel_guc_ct.h"
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2018-03-27 02:48:28 +07:00
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#ifdef CONFIG_DRM_I915_DEBUG_GUC
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#define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__)
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#else
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#define CT_DEBUG_DRIVER(...) do { } while (0)
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#endif
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2018-03-27 19:14:39 +07:00
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struct ct_request {
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struct list_head link;
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u32 fence;
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u32 status;
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u32 response_len;
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u32 *response_buf;
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};
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2018-03-27 02:48:26 +07:00
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struct ct_incoming_request {
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struct list_head link;
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u32 msg[];
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};
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2017-05-26 18:13:25 +07:00
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enum { CTB_SEND = 0, CTB_RECV = 1 };
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enum { CTB_OWNER_HOST = 0 };
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2018-03-27 02:48:26 +07:00
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static void ct_incoming_request_worker_func(struct work_struct *w);
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2018-03-20 23:20:20 +07:00
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/**
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* intel_guc_ct_init_early - Initialize CT state without requiring device access
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* @ct: pointer to CT struct
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*/
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2017-05-26 18:13:25 +07:00
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void intel_guc_ct_init_early(struct intel_guc_ct *ct)
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{
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/* we're using static channel owners */
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ct->host_channel.owner = CTB_OWNER_HOST;
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2018-03-27 19:14:39 +07:00
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spin_lock_init(&ct->lock);
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INIT_LIST_HEAD(&ct->pending_requests);
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2018-03-27 02:48:26 +07:00
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INIT_LIST_HEAD(&ct->incoming_requests);
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INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
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2017-05-26 18:13:25 +07:00
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}
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2018-03-20 23:20:20 +07:00
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static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
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{
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return container_of(ct, struct intel_guc, ct);
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}
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2017-05-26 18:13:25 +07:00
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static inline const char *guc_ct_buffer_type_to_str(u32 type)
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{
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switch (type) {
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case INTEL_GUC_CT_BUFFER_TYPE_SEND:
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return "SEND";
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case INTEL_GUC_CT_BUFFER_TYPE_RECV:
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return "RECV";
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default:
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return "<invalid>";
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}
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}
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static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
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u32 cmds_addr, u32 size, u32 owner)
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{
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2018-03-27 02:48:28 +07:00
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CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
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desc, cmds_addr, size, owner);
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2017-05-26 18:13:25 +07:00
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memset(desc, 0, sizeof(*desc));
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desc->addr = cmds_addr;
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desc->size = size;
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desc->owner = owner;
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}
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static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
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{
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2018-03-27 02:48:28 +07:00
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CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
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desc, desc->head, desc->tail);
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2017-05-26 18:13:25 +07:00
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desc->head = 0;
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desc->tail = 0;
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desc->is_in_error = 0;
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}
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static int guc_action_register_ct_buffer(struct intel_guc *guc,
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u32 desc_addr,
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u32 type)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER,
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desc_addr,
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sizeof(struct guc_ct_buffer_desc),
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type
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};
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int err;
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/* Can't use generic send(), CT registration must go over MMIO */
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2018-03-27 02:48:20 +07:00
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err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
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2017-05-26 18:13:25 +07:00
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if (err)
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DRM_ERROR("CT: register %s buffer failed; err=%d\n",
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guc_ct_buffer_type_to_str(type), err);
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return err;
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}
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static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
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u32 owner,
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u32 type)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
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owner,
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type
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};
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int err;
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/* Can't use generic send(), CT deregistration must go over MMIO */
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2018-03-27 02:48:20 +07:00
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err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
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2017-05-26 18:13:25 +07:00
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if (err)
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DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
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guc_ct_buffer_type_to_str(type), owner, err);
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return err;
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}
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static bool ctch_is_open(struct intel_guc_ct_channel *ctch)
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{
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return ctch->vma != NULL;
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}
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static int ctch_init(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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struct i915_vma *vma;
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void *blob;
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int err;
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int i;
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GEM_BUG_ON(ctch->vma);
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/* We allocate 1 page to hold both descriptors and both buffers.
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* ___________.....................
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* |desc (SEND)| :
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* |___________| PAGE/4
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* :___________....................:
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* |desc (RECV)| :
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* |___________| PAGE/4
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* :_______________________________:
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* |cmds (SEND) |
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* | PAGE/4
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* |_______________________________|
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* |cmds (RECV) |
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* | PAGE/4
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* |_______________________________|
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*
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* Each message can use a maximum of 32 dwords and we don't expect to
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* have more than 1 in flight at any time, so we have enough space.
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* Some logic further ahead will rely on the fact that there is only 1
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* page and that it is always mapped, so if the size is changed the
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* other code will need updating as well.
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*/
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/* allocate vma */
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vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_out;
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}
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ctch->vma = vma;
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/* map first page */
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blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(blob)) {
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err = PTR_ERR(blob);
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goto err_vma;
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}
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2018-03-27 02:48:28 +07:00
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CT_DEBUG_DRIVER("CT: vma base=%#x\n",
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intel_guc_ggtt_offset(guc, ctch->vma));
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2017-05-26 18:13:25 +07:00
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/* store pointers to desc and cmds */
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for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
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GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
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ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
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ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
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}
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return 0;
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err_vma:
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2018-07-21 19:50:37 +07:00
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i915_vma_unpin_and_release(&ctch->vma, 0);
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2017-05-26 18:13:25 +07:00
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err_out:
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2018-03-27 02:48:28 +07:00
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CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
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ctch->owner, err);
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2017-05-26 18:13:25 +07:00
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return err;
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}
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static void ctch_fini(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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2018-07-21 19:50:37 +07:00
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i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
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2017-05-26 18:13:25 +07:00
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}
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static int ctch_open(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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u32 base;
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int err;
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int i;
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2018-03-27 02:48:28 +07:00
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CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n",
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ctch->owner, yesno(ctch_is_open(ctch)));
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2017-05-26 18:13:25 +07:00
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if (!ctch->vma) {
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err = ctch_init(guc, ctch);
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if (unlikely(err))
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goto err_out;
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2017-11-06 20:51:54 +07:00
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GEM_BUG_ON(!ctch->vma);
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2017-05-26 18:13:25 +07:00
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}
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/* vma should be already allocated and map'ed */
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2018-03-14 07:32:49 +07:00
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base = intel_guc_ggtt_offset(guc, ctch->vma);
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2017-05-26 18:13:25 +07:00
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/* (re)initialize descriptors
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* cmds buffers are in the second half of the blob page
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*/
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for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
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GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
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guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
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base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
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PAGE_SIZE/4,
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ctch->owner);
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}
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/* register buffers, starting wirh RECV buffer
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* descriptors are in first half of the blob
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*/
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err = guc_action_register_ct_buffer(guc,
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base + PAGE_SIZE/4 * CTB_RECV,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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if (unlikely(err))
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goto err_fini;
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err = guc_action_register_ct_buffer(guc,
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base + PAGE_SIZE/4 * CTB_SEND,
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INTEL_GUC_CT_BUFFER_TYPE_SEND);
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if (unlikely(err))
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goto err_deregister;
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return 0;
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err_deregister:
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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err_fini:
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ctch_fini(guc, ctch);
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err_out:
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DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
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return err;
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}
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static void ctch_close(struct intel_guc *guc,
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struct intel_guc_ct_channel *ctch)
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{
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GEM_BUG_ON(!ctch_is_open(ctch));
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_SEND);
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guc_action_deregister_ct_buffer(guc,
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ctch->owner,
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INTEL_GUC_CT_BUFFER_TYPE_RECV);
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ctch_fini(guc, ctch);
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}
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static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
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{
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/* For now it's trivial */
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return ++ctch->next_fence;
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}
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2018-03-27 02:48:23 +07:00
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/**
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* DOC: CTB Host to GuC request
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*
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* Format of the CTB Host to GuC request message is as follows::
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*
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* +------------+---------+---------+---------+---------+
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* | msg[0] | [1] | [2] | ... | [n-1] |
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* +------------+---------+---------+---------+---------+
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* | MESSAGE | MESSAGE PAYLOAD |
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* + HEADER +---------+---------+---------+---------+
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* | | 0 | 1 | ... | n |
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* +============+=========+=========+=========+=========+
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* | len >= 1 | FENCE | request specific data |
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* +------+-----+---------+---------+---------+---------+
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*
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* ^-----------------len-------------------^
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*/
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2017-05-26 18:13:25 +07:00
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static int ctb_write(struct intel_guc_ct_buffer *ctb,
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const u32 *action,
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u32 len /* in dwords */,
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2018-03-27 19:14:39 +07:00
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u32 fence,
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bool want_response)
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2017-05-26 18:13:25 +07:00
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{
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struct guc_ct_buffer_desc *desc = ctb->desc;
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u32 head = desc->head / 4; /* in dwords */
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u32 tail = desc->tail / 4; /* in dwords */
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u32 size = desc->size / 4; /* in dwords */
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u32 used; /* in dwords */
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u32 header;
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u32 *cmds = ctb->cmds;
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unsigned int i;
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GEM_BUG_ON(desc->size % 4);
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GEM_BUG_ON(desc->head % 4);
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GEM_BUG_ON(desc->tail % 4);
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GEM_BUG_ON(tail >= size);
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/*
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* tail == head condition indicates empty. GuC FW does not support
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* using up the entire buffer to get tail == head meaning full.
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|
|
|
*/
|
|
|
|
if (tail < head)
|
|
|
|
used = (size - head) + tail;
|
|
|
|
else
|
|
|
|
used = tail - head;
|
|
|
|
|
|
|
|
/* make sure there is a space including extra dw for the fence */
|
|
|
|
if (unlikely(used + len + 1 >= size))
|
|
|
|
return -ENOSPC;
|
|
|
|
|
2018-03-27 02:48:23 +07:00
|
|
|
/*
|
|
|
|
* Write the message. The format is the following:
|
2017-05-26 18:13:25 +07:00
|
|
|
* DW0: header (including action code)
|
|
|
|
* DW1: fence
|
|
|
|
* DW2+: action data
|
|
|
|
*/
|
|
|
|
header = (len << GUC_CT_MSG_LEN_SHIFT) |
|
|
|
|
(GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
|
2018-03-27 19:14:39 +07:00
|
|
|
(want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
|
2017-05-26 18:13:25 +07:00
|
|
|
(action[0] << GUC_CT_MSG_ACTION_SHIFT);
|
|
|
|
|
2018-04-10 18:14:17 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: writing %*ph %*ph %*ph\n",
|
2018-03-27 02:48:28 +07:00
|
|
|
4, &header, 4, &fence,
|
|
|
|
4 * (len - 1), &action[1]);
|
|
|
|
|
2017-05-26 18:13:25 +07:00
|
|
|
cmds[tail] = header;
|
|
|
|
tail = (tail + 1) % size;
|
|
|
|
|
|
|
|
cmds[tail] = fence;
|
|
|
|
tail = (tail + 1) % size;
|
|
|
|
|
|
|
|
for (i = 1; i < len; i++) {
|
|
|
|
cmds[tail] = action[i];
|
|
|
|
tail = (tail + 1) % size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* now update desc tail (back in bytes) */
|
|
|
|
desc->tail = tail * 4;
|
|
|
|
GEM_BUG_ON(desc->tail > desc->size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-03-27 02:48:24 +07:00
|
|
|
/**
|
|
|
|
* wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
|
|
|
|
* @desc: buffer descriptor
|
2017-05-26 18:13:25 +07:00
|
|
|
* @fence: response fence
|
|
|
|
* @status: placeholder for status
|
2018-03-27 02:48:24 +07:00
|
|
|
*
|
|
|
|
* Guc will update CT buffer descriptor with new fence and status
|
|
|
|
* after processing the command identified by the fence. Wait for
|
|
|
|
* specified fence and then read from the descriptor status of the
|
|
|
|
* command.
|
|
|
|
*
|
|
|
|
* Return:
|
|
|
|
* * 0 response received (status is valid)
|
|
|
|
* * -ETIMEDOUT no response within hardcoded timeout
|
|
|
|
* * -EPROTO no response, CT buffer is in error
|
2017-05-26 18:13:25 +07:00
|
|
|
*/
|
2018-03-27 02:48:24 +07:00
|
|
|
static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
|
|
|
|
u32 fence,
|
|
|
|
u32 *status)
|
2017-05-26 18:13:25 +07:00
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fast commands should complete in less than 10us, so sample quickly
|
|
|
|
* up to that length of time, then switch to a slower sleep-wait loop.
|
|
|
|
* No GuC command should ever take longer than 10ms.
|
|
|
|
*/
|
|
|
|
#define done (READ_ONCE(desc->fence) == fence)
|
|
|
|
err = wait_for_us(done, 10);
|
|
|
|
if (err)
|
|
|
|
err = wait_for(done, 10);
|
|
|
|
#undef done
|
|
|
|
|
|
|
|
if (unlikely(err)) {
|
|
|
|
DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
|
|
|
|
fence, desc->fence);
|
|
|
|
|
|
|
|
if (WARN_ON(desc->is_in_error)) {
|
|
|
|
/* Something went wrong with the messaging, try to reset
|
|
|
|
* the buffer and hope for the best
|
|
|
|
*/
|
|
|
|
guc_ct_buffer_desc_reset(desc);
|
|
|
|
err = -EPROTO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
*status = desc->status;
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
/**
|
|
|
|
* wait_for_ct_request_update - Wait for CT request state update.
|
|
|
|
* @req: pointer to pending request
|
|
|
|
* @status: placeholder for status
|
|
|
|
*
|
|
|
|
* For each sent request, Guc shall send bac CT response message.
|
|
|
|
* Our message handler will update status of tracked request once
|
|
|
|
* response message with given fence is received. Wait here and
|
|
|
|
* check for valid response status value.
|
|
|
|
*
|
|
|
|
* Return:
|
|
|
|
* * 0 response received (status is valid)
|
|
|
|
* * -ETIMEDOUT no response within hardcoded timeout
|
|
|
|
*/
|
|
|
|
static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fast commands should complete in less than 10us, so sample quickly
|
|
|
|
* up to that length of time, then switch to a slower sleep-wait loop.
|
|
|
|
* No GuC command should ever take longer than 10ms.
|
|
|
|
*/
|
|
|
|
#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
|
|
|
|
err = wait_for_us(done, 10);
|
|
|
|
if (err)
|
|
|
|
err = wait_for(done, 10);
|
|
|
|
#undef done
|
|
|
|
|
|
|
|
if (unlikely(err))
|
|
|
|
DRM_ERROR("CT: fence %u err %d\n", req->fence, err);
|
|
|
|
|
|
|
|
*status = req->status;
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ctch_send(struct intel_guc_ct *ct,
|
2017-05-26 18:13:25 +07:00
|
|
|
struct intel_guc_ct_channel *ctch,
|
|
|
|
const u32 *action,
|
|
|
|
u32 len,
|
2018-03-27 19:14:39 +07:00
|
|
|
u32 *response_buf,
|
|
|
|
u32 response_buf_size,
|
2017-05-26 18:13:25 +07:00
|
|
|
u32 *status)
|
|
|
|
{
|
|
|
|
struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
|
|
|
|
struct guc_ct_buffer_desc *desc = ctb->desc;
|
2018-03-27 19:14:39 +07:00
|
|
|
struct ct_request request;
|
|
|
|
unsigned long flags;
|
2017-05-26 18:13:25 +07:00
|
|
|
u32 fence;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
GEM_BUG_ON(!ctch_is_open(ctch));
|
|
|
|
GEM_BUG_ON(!len);
|
|
|
|
GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
|
2018-03-27 19:14:39 +07:00
|
|
|
GEM_BUG_ON(!response_buf && response_buf_size);
|
2017-05-26 18:13:25 +07:00
|
|
|
|
|
|
|
fence = ctch_get_next_fence(ctch);
|
2018-03-27 19:14:39 +07:00
|
|
|
request.fence = fence;
|
|
|
|
request.status = 0;
|
|
|
|
request.response_len = response_buf_size;
|
|
|
|
request.response_buf = response_buf;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ct->lock, flags);
|
|
|
|
list_add_tail(&request.link, &ct->pending_requests);
|
|
|
|
spin_unlock_irqrestore(&ct->lock, flags);
|
|
|
|
|
|
|
|
err = ctb_write(ctb, action, len, fence, !!response_buf);
|
2017-05-26 18:13:25 +07:00
|
|
|
if (unlikely(err))
|
2018-03-27 19:14:39 +07:00
|
|
|
goto unlink;
|
2017-05-26 18:13:25 +07:00
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
intel_guc_notify(ct_to_guc(ct));
|
2017-05-26 18:13:25 +07:00
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
if (response_buf)
|
|
|
|
err = wait_for_ct_request_update(&request, status);
|
|
|
|
else
|
|
|
|
err = wait_for_ctb_desc_update(desc, fence, status);
|
2017-05-26 18:13:25 +07:00
|
|
|
if (unlikely(err))
|
2018-03-27 19:14:39 +07:00
|
|
|
goto unlink;
|
|
|
|
|
|
|
|
if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
|
|
|
|
err = -EIO;
|
|
|
|
goto unlink;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (response_buf) {
|
|
|
|
/* There shall be no data in the status */
|
|
|
|
WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
|
|
|
|
/* Return actual response len */
|
|
|
|
err = request.response_len;
|
|
|
|
} else {
|
|
|
|
/* There shall be no response payload */
|
|
|
|
WARN_ON(request.response_len);
|
|
|
|
/* Return data decoded from the status dword */
|
|
|
|
err = INTEL_GUC_MSG_TO_DATA(*status);
|
|
|
|
}
|
2018-03-27 02:48:19 +07:00
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
unlink:
|
|
|
|
spin_lock_irqsave(&ct->lock, flags);
|
|
|
|
list_del(&request.link);
|
|
|
|
spin_unlock_irqrestore(&ct->lock, flags);
|
|
|
|
|
|
|
|
return err;
|
2017-05-26 18:13:25 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Command Transport (CT) buffer based GuC send function.
|
|
|
|
*/
|
2018-03-27 02:48:20 +07:00
|
|
|
static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
|
|
|
|
u32 *response_buf, u32 response_buf_size)
|
2017-05-26 18:13:25 +07:00
|
|
|
{
|
2018-03-27 19:14:39 +07:00
|
|
|
struct intel_guc_ct *ct = &guc->ct;
|
|
|
|
struct intel_guc_ct_channel *ctch = &ct->host_channel;
|
2017-05-26 18:13:25 +07:00
|
|
|
u32 status = ~0; /* undefined */
|
2018-03-27 02:48:19 +07:00
|
|
|
int ret;
|
2017-05-26 18:13:25 +07:00
|
|
|
|
|
|
|
mutex_lock(&guc->send_mutex);
|
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
|
|
|
|
&status);
|
2018-03-27 02:48:19 +07:00
|
|
|
if (unlikely(ret < 0)) {
|
2017-05-26 18:13:25 +07:00
|
|
|
DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
|
2018-03-27 02:48:19 +07:00
|
|
|
action[0], ret, status);
|
2018-03-27 02:48:28 +07:00
|
|
|
} else if (unlikely(ret)) {
|
|
|
|
CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
|
|
|
|
action[0], ret, ret);
|
2017-05-26 18:13:25 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&guc->send_mutex);
|
2018-03-27 02:48:19 +07:00
|
|
|
return ret;
|
2017-05-26 18:13:25 +07:00
|
|
|
}
|
|
|
|
|
2018-03-27 02:48:23 +07:00
|
|
|
static inline unsigned int ct_header_get_len(u32 header)
|
|
|
|
{
|
|
|
|
return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int ct_header_get_action(u32 header)
|
|
|
|
{
|
|
|
|
return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool ct_header_is_response(u32 header)
|
|
|
|
{
|
|
|
|
return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
|
|
|
|
{
|
|
|
|
struct guc_ct_buffer_desc *desc = ctb->desc;
|
|
|
|
u32 head = desc->head / 4; /* in dwords */
|
|
|
|
u32 tail = desc->tail / 4; /* in dwords */
|
|
|
|
u32 size = desc->size / 4; /* in dwords */
|
|
|
|
u32 *cmds = ctb->cmds;
|
|
|
|
s32 available; /* in dwords */
|
|
|
|
unsigned int len;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
GEM_BUG_ON(desc->size % 4);
|
|
|
|
GEM_BUG_ON(desc->head % 4);
|
|
|
|
GEM_BUG_ON(desc->tail % 4);
|
|
|
|
GEM_BUG_ON(tail >= size);
|
|
|
|
GEM_BUG_ON(head >= size);
|
|
|
|
|
|
|
|
/* tail == head condition indicates empty */
|
|
|
|
available = tail - head;
|
|
|
|
if (unlikely(available == 0))
|
|
|
|
return -ENODATA;
|
|
|
|
|
|
|
|
/* beware of buffer wrap case */
|
|
|
|
if (unlikely(available < 0))
|
|
|
|
available += size;
|
2018-03-27 02:48:28 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail);
|
2018-03-27 02:48:23 +07:00
|
|
|
GEM_BUG_ON(available < 0);
|
|
|
|
|
|
|
|
data[0] = cmds[head];
|
|
|
|
head = (head + 1) % size;
|
|
|
|
|
|
|
|
/* message len with header */
|
|
|
|
len = ct_header_get_len(data[0]) + 1;
|
|
|
|
if (unlikely(len > (u32)available)) {
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: incomplete message %*ph %*ph %*ph\n",
|
2018-03-27 02:48:23 +07:00
|
|
|
4, data,
|
|
|
|
4 * (head + available - 1 > size ?
|
|
|
|
size - head : available - 1), &cmds[head],
|
|
|
|
4 * (head + available - 1 > size ?
|
|
|
|
available - 1 - size + head : 0), &cmds[0]);
|
|
|
|
return -EPROTO;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 1; i < len; i++) {
|
|
|
|
data[i] = cmds[head];
|
|
|
|
head = (head + 1) % size;
|
|
|
|
}
|
2018-04-10 18:14:17 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: received %*ph\n", 4 * len, data);
|
2018-03-27 02:48:23 +07:00
|
|
|
|
|
|
|
desc->head = head * 4;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* DOC: CTB GuC to Host response
|
|
|
|
*
|
|
|
|
* Format of the CTB GuC to Host response message is as follows::
|
|
|
|
*
|
|
|
|
* +------------+---------+---------+---------+---------+---------+
|
|
|
|
* | msg[0] | [1] | [2] | [3] | ... | [n-1] |
|
|
|
|
* +------------+---------+---------+---------+---------+---------+
|
|
|
|
* | MESSAGE | MESSAGE PAYLOAD |
|
|
|
|
* + HEADER +---------+---------+---------+---------+---------+
|
|
|
|
* | | 0 | 1 | 2 | ... | n |
|
|
|
|
* +============+=========+=========+=========+=========+=========+
|
|
|
|
* | len >= 2 | FENCE | STATUS | response specific data |
|
|
|
|
* +------+-----+---------+---------+---------+---------+---------+
|
|
|
|
*
|
|
|
|
* ^-----------------------len-----------------------^
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
|
|
|
|
{
|
|
|
|
u32 header = msg[0];
|
|
|
|
u32 len = ct_header_get_len(header);
|
|
|
|
u32 msglen = len + 1; /* total message length including header */
|
|
|
|
u32 fence;
|
|
|
|
u32 status;
|
2018-03-27 19:14:39 +07:00
|
|
|
u32 datalen;
|
|
|
|
struct ct_request *req;
|
|
|
|
bool found = false;
|
2018-03-27 02:48:23 +07:00
|
|
|
|
|
|
|
GEM_BUG_ON(!ct_header_is_response(header));
|
2018-03-27 19:14:39 +07:00
|
|
|
GEM_BUG_ON(!in_irq());
|
2018-03-27 02:48:23 +07:00
|
|
|
|
|
|
|
/* Response payload shall at least include fence and status */
|
|
|
|
if (unlikely(len < 2)) {
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
|
2018-03-27 02:48:23 +07:00
|
|
|
return -EPROTO;
|
|
|
|
}
|
|
|
|
|
|
|
|
fence = msg[1];
|
|
|
|
status = msg[2];
|
2018-03-27 19:14:39 +07:00
|
|
|
datalen = len - 2;
|
2018-03-27 02:48:23 +07:00
|
|
|
|
|
|
|
/* Format of the status follows RESPONSE message */
|
|
|
|
if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
|
2018-03-27 02:48:23 +07:00
|
|
|
return -EPROTO;
|
|
|
|
}
|
|
|
|
|
2018-03-27 02:48:28 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
|
|
|
|
|
2018-03-27 19:14:39 +07:00
|
|
|
spin_lock(&ct->lock);
|
|
|
|
list_for_each_entry(req, &ct->pending_requests, link) {
|
|
|
|
if (unlikely(fence != req->fence)) {
|
2018-03-27 02:48:28 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: request %u awaits response\n",
|
|
|
|
req->fence);
|
2018-03-27 19:14:39 +07:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (unlikely(datalen > req->response_len)) {
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: response %u too long %*ph\n",
|
2018-03-27 19:14:39 +07:00
|
|
|
req->fence, 4 * msglen, msg);
|
|
|
|
datalen = 0;
|
|
|
|
}
|
|
|
|
if (datalen)
|
|
|
|
memcpy(req->response_buf, msg + 3, 4 * datalen);
|
|
|
|
req->response_len = datalen;
|
|
|
|
WRITE_ONCE(req->status, status);
|
|
|
|
found = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spin_unlock(&ct->lock);
|
|
|
|
|
|
|
|
if (!found)
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
|
2018-03-27 02:48:23 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-03-27 02:48:26 +07:00
|
|
|
static void ct_process_request(struct intel_guc_ct *ct,
|
|
|
|
u32 action, u32 len, const u32 *payload)
|
|
|
|
{
|
2018-03-28 04:41:24 +07:00
|
|
|
struct intel_guc *guc = ct_to_guc(ct);
|
|
|
|
|
2018-04-10 18:14:17 +07:00
|
|
|
CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload);
|
2018-03-27 02:48:28 +07:00
|
|
|
|
2018-03-27 02:48:26 +07:00
|
|
|
switch (action) {
|
2018-03-28 04:41:24 +07:00
|
|
|
case INTEL_GUC_ACTION_DEFAULT:
|
|
|
|
if (unlikely(len < 1))
|
|
|
|
goto fail_unexpected;
|
|
|
|
intel_guc_to_host_process_recv_msg(guc, *payload);
|
|
|
|
break;
|
|
|
|
|
2018-03-27 02:48:26 +07:00
|
|
|
default:
|
2018-03-28 04:41:24 +07:00
|
|
|
fail_unexpected:
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: unexpected request %x %*ph\n",
|
2018-03-27 02:48:26 +07:00
|
|
|
action, 4 * len, payload);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct ct_incoming_request *request;
|
|
|
|
u32 header;
|
|
|
|
u32 *payload;
|
|
|
|
bool done;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ct->lock, flags);
|
|
|
|
request = list_first_entry_or_null(&ct->incoming_requests,
|
|
|
|
struct ct_incoming_request, link);
|
|
|
|
if (request)
|
|
|
|
list_del(&request->link);
|
|
|
|
done = !!list_empty(&ct->incoming_requests);
|
|
|
|
spin_unlock_irqrestore(&ct->lock, flags);
|
|
|
|
|
|
|
|
if (!request)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
header = request->msg[0];
|
|
|
|
payload = &request->msg[1];
|
|
|
|
ct_process_request(ct,
|
|
|
|
ct_header_get_action(header),
|
|
|
|
ct_header_get_len(header),
|
|
|
|
payload);
|
|
|
|
|
|
|
|
kfree(request);
|
|
|
|
return done;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ct_incoming_request_worker_func(struct work_struct *w)
|
|
|
|
{
|
|
|
|
struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
|
|
|
|
bool done;
|
|
|
|
|
|
|
|
done = ct_process_incoming_requests(ct);
|
|
|
|
if (!done)
|
|
|
|
queue_work(system_unbound_wq, &ct->worker);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* DOC: CTB GuC to Host request
|
|
|
|
*
|
|
|
|
* Format of the CTB GuC to Host request message is as follows::
|
|
|
|
*
|
|
|
|
* +------------+---------+---------+---------+---------+---------+
|
|
|
|
* | msg[0] | [1] | [2] | [3] | ... | [n-1] |
|
|
|
|
* +------------+---------+---------+---------+---------+---------+
|
|
|
|
* | MESSAGE | MESSAGE PAYLOAD |
|
|
|
|
* + HEADER +---------+---------+---------+---------+---------+
|
|
|
|
* | | 0 | 1 | 2 | ... | n |
|
|
|
|
* +============+=========+=========+=========+=========+=========+
|
|
|
|
* | len | request specific data |
|
|
|
|
* +------+-----+---------+---------+---------+---------+---------+
|
|
|
|
*
|
|
|
|
* ^-----------------------len-----------------------^
|
|
|
|
*/
|
|
|
|
|
2018-03-27 02:48:23 +07:00
|
|
|
static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
|
|
|
|
{
|
|
|
|
u32 header = msg[0];
|
2018-03-27 02:48:26 +07:00
|
|
|
u32 len = ct_header_get_len(header);
|
|
|
|
u32 msglen = len + 1; /* total message length including header */
|
|
|
|
struct ct_incoming_request *request;
|
|
|
|
unsigned long flags;
|
2018-03-27 02:48:23 +07:00
|
|
|
|
|
|
|
GEM_BUG_ON(ct_header_is_response(header));
|
|
|
|
|
2018-03-27 02:48:26 +07:00
|
|
|
request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
|
|
|
|
if (unlikely(!request)) {
|
2018-04-10 18:14:17 +07:00
|
|
|
DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
|
2018-03-27 02:48:26 +07:00
|
|
|
return 0; /* XXX: -ENOMEM ? */
|
|
|
|
}
|
|
|
|
memcpy(request->msg, msg, 4 * msglen);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ct->lock, flags);
|
|
|
|
list_add_tail(&request->link, &ct->incoming_requests);
|
|
|
|
spin_unlock_irqrestore(&ct->lock, flags);
|
|
|
|
|
|
|
|
queue_work(system_unbound_wq, &ct->worker);
|
2018-03-27 02:48:23 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ct_process_host_channel(struct intel_guc_ct *ct)
|
|
|
|
{
|
|
|
|
struct intel_guc_ct_channel *ctch = &ct->host_channel;
|
|
|
|
struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
|
|
|
|
u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (!ctch_is_open(ctch))
|
|
|
|
return;
|
|
|
|
|
|
|
|
do {
|
|
|
|
err = ctb_read(ctb, msg);
|
|
|
|
if (err)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (ct_header_is_response(msg[0]))
|
|
|
|
err = ct_handle_response(ct, msg);
|
|
|
|
else
|
|
|
|
err = ct_handle_request(ct, msg);
|
|
|
|
} while (!err);
|
|
|
|
|
|
|
|
if (GEM_WARN_ON(err == -EPROTO)) {
|
|
|
|
DRM_ERROR("CT: corrupted message detected!\n");
|
|
|
|
ctb->desc->is_in_error = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When we're communicating with the GuC over CT, GuC uses events
|
|
|
|
* to notify us about new messages being posted on the RECV buffer.
|
|
|
|
*/
|
|
|
|
static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
|
|
|
|
{
|
|
|
|
struct intel_guc_ct *ct = &guc->ct;
|
|
|
|
|
|
|
|
ct_process_host_channel(ct);
|
|
|
|
}
|
|
|
|
|
2017-05-26 18:13:25 +07:00
|
|
|
/**
|
2018-03-20 23:20:20 +07:00
|
|
|
* intel_guc_ct_enable - Enable buffer based command transport.
|
|
|
|
* @ct: pointer to CT struct
|
|
|
|
*
|
2017-05-26 18:13:25 +07:00
|
|
|
* Shall only be called for platforms with HAS_GUC_CT.
|
2018-03-20 23:20:20 +07:00
|
|
|
*
|
|
|
|
* Return: 0 on success, a negative errno code on failure.
|
2017-05-26 18:13:25 +07:00
|
|
|
*/
|
2018-03-20 23:20:20 +07:00
|
|
|
int intel_guc_ct_enable(struct intel_guc_ct *ct)
|
2017-05-26 18:13:25 +07:00
|
|
|
{
|
2018-03-20 23:20:20 +07:00
|
|
|
struct intel_guc *guc = ct_to_guc(ct);
|
|
|
|
struct drm_i915_private *i915 = guc_to_i915(guc);
|
|
|
|
struct intel_guc_ct_channel *ctch = &ct->host_channel;
|
2017-05-26 18:13:25 +07:00
|
|
|
int err;
|
|
|
|
|
2018-03-20 23:20:20 +07:00
|
|
|
GEM_BUG_ON(!HAS_GUC_CT(i915));
|
2017-05-26 18:13:25 +07:00
|
|
|
|
|
|
|
err = ctch_open(guc, ctch);
|
|
|
|
if (unlikely(err))
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Switch into cmd transport buffer based send() */
|
|
|
|
guc->send = intel_guc_send_ct;
|
2018-03-27 02:48:23 +07:00
|
|
|
guc->handler = intel_guc_to_host_event_handler_ct;
|
2017-05-26 18:13:25 +07:00
|
|
|
DRM_INFO("CT: %s\n", enableddisabled(true));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2018-03-20 23:20:20 +07:00
|
|
|
* intel_guc_ct_disable - Disable buffer based command transport.
|
|
|
|
* @ct: pointer to CT struct
|
|
|
|
*
|
2017-05-26 18:13:25 +07:00
|
|
|
* Shall only be called for platforms with HAS_GUC_CT.
|
|
|
|
*/
|
2018-03-20 23:20:20 +07:00
|
|
|
void intel_guc_ct_disable(struct intel_guc_ct *ct)
|
2017-05-26 18:13:25 +07:00
|
|
|
{
|
2018-03-20 23:20:20 +07:00
|
|
|
struct intel_guc *guc = ct_to_guc(ct);
|
|
|
|
struct drm_i915_private *i915 = guc_to_i915(guc);
|
|
|
|
struct intel_guc_ct_channel *ctch = &ct->host_channel;
|
2017-05-26 18:13:25 +07:00
|
|
|
|
2018-03-20 23:20:20 +07:00
|
|
|
GEM_BUG_ON(!HAS_GUC_CT(i915));
|
2017-05-26 18:13:25 +07:00
|
|
|
|
|
|
|
if (!ctch_is_open(ctch))
|
|
|
|
return;
|
|
|
|
|
|
|
|
ctch_close(guc, ctch);
|
|
|
|
|
|
|
|
/* Disable send */
|
|
|
|
guc->send = intel_guc_send_nop;
|
2018-03-27 02:48:23 +07:00
|
|
|
guc->handler = intel_guc_to_host_event_handler_nop;
|
2017-05-26 18:13:25 +07:00
|
|
|
DRM_INFO("CT: %s\n", enableddisabled(false));
|
|
|
|
}
|