2010-08-24 10:24:12 +07:00
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/*
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* Linux network driver for Brocade Converged Network Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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2011-08-30 22:27:41 +07:00
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/*
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* Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*/
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2010-08-24 10:24:12 +07:00
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#ifndef __BNA_H__
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#define __BNA_H__
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2011-08-30 22:27:41 +07:00
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#include "bfa_defs.h"
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2010-08-24 10:24:12 +07:00
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#include "bfa_ioc.h"
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2011-08-30 22:27:41 +07:00
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#include "bfi_enet.h"
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2010-08-24 10:24:12 +07:00
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#include "bna_types.h"
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2010-10-05 22:46:05 +07:00
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extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
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2010-08-24 10:24:12 +07:00
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2012-07-10 17:56:59 +07:00
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/* Macros and constants */
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2010-08-24 10:24:12 +07:00
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#define BNA_IOC_TIMER_FREQ 200
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/* Log string size */
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#define BNA_MESSAGE_SIZE 256
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
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#define bna_is_small_rxq(_id) ((_id) & 0x1)
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2010-08-24 10:24:12 +07:00
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#define BNA_MAC_IS_EQUAL(_mac1, _mac2) \
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(!memcmp((_mac1), (_mac2), sizeof(mac_t)))
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#define BNA_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
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#define BNA_TO_POWER_OF_2(x) \
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do { \
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int _shift = 0; \
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while ((x) && (x) != 1) { \
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(x) >>= 1; \
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_shift++; \
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} \
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(x) <<= _shift; \
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} while (0)
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#define BNA_TO_POWER_OF_2_HIGH(x) \
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do { \
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int n = 1; \
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while (n < (x)) \
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n <<= 1; \
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(x) = n; \
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} while (0)
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/*
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* input : _addr-> os dma addr in host endian format,
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* output : _bna_dma_addr-> pointer to hw dma addr
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*/
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#define BNA_SET_DMA_ADDR(_addr, _bna_dma_addr) \
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do { \
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u64 tmp_addr = \
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cpu_to_be64((u64)(_addr)); \
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(_bna_dma_addr)->msb = ((struct bna_dma_addr *)&tmp_addr)->msb; \
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(_bna_dma_addr)->lsb = ((struct bna_dma_addr *)&tmp_addr)->lsb; \
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} while (0)
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/*
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* input : _bna_dma_addr-> pointer to hw dma addr
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* output : _addr-> os dma addr in host endian format
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*/
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#define BNA_GET_DMA_ADDR(_bna_dma_addr, _addr) \
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do { \
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(_addr) = ((((u64)ntohl((_bna_dma_addr)->msb))) << 32) \
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| ((ntohl((_bna_dma_addr)->lsb) & 0xffffffff)); \
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} while (0)
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#define containing_rec(addr, type, field) \
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2011-07-22 15:07:41 +07:00
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((type *)((unsigned char *)(addr) - \
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2010-08-24 10:24:12 +07:00
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(unsigned char *)(&((type *)0)->field)))
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#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
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/* TxQ element is 64 bytes */
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#define BNA_TXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 6)
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#define BNA_TXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 6)
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#define BNA_TXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
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{ \
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unsigned int page_index; /* index within a page */ \
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void *page_addr; \
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2011-07-22 15:07:41 +07:00
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page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
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(_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
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2010-08-24 10:24:12 +07:00
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page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\
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(_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
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}
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/* RxQ element is 8 bytes */
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#define BNA_RXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 3)
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#define BNA_RXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 3)
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#define BNA_RXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
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{ \
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unsigned int page_index; /* index within a page */ \
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void *page_addr; \
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page_index = (_qe_idx) & (BNA_RXQ_PAGE_INDEX_MAX - 1); \
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(_qe_ptr_range) = (BNA_RXQ_PAGE_INDEX_MAX - page_index); \
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page_addr = (_qpt_ptr)[((_qe_idx) >> \
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BNA_RXQ_PAGE_INDEX_MAX_SHIFT)]; \
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(_qe_ptr) = &((struct bna_rxq_entry *)(page_addr))[page_index]; \
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}
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/* CQ element is 16 bytes */
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#define BNA_CQ_PAGE_INDEX_MAX (PAGE_SIZE >> 4)
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#define BNA_CQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 4)
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#define BNA_CQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
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{ \
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unsigned int page_index; /* index within a page */ \
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void *page_addr; \
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\
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page_index = (_qe_idx) & (BNA_CQ_PAGE_INDEX_MAX - 1); \
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(_qe_ptr_range) = (BNA_CQ_PAGE_INDEX_MAX - page_index); \
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page_addr = (_qpt_ptr)[((_qe_idx) >> \
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BNA_CQ_PAGE_INDEX_MAX_SHIFT)]; \
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(_qe_ptr) = &((struct bna_cq_entry *)(page_addr))[page_index];\
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}
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#define BNA_QE_INDX_2_PTR(_cast, _qe_idx, _q_base) \
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(&((_cast *)(_q_base))[(_qe_idx)])
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#define BNA_QE_INDX_RANGE(_qe_idx, _q_depth) ((_q_depth) - (_qe_idx))
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#define BNA_QE_INDX_ADD(_qe_idx, _qe_num, _q_depth) \
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((_qe_idx) = ((_qe_idx) + (_qe_num)) & ((_q_depth) - 1))
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2012-12-11 19:24:51 +07:00
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#define BNA_QE_INDX_INC(_idx, _q_depth) BNA_QE_INDX_ADD(_idx, 1, _q_depth)
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2010-08-24 10:24:12 +07:00
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#define BNA_Q_INDEX_CHANGE(_old_idx, _updated_idx, _q_depth) \
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(((_updated_idx) - (_old_idx)) & ((_q_depth) - 1))
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#define BNA_QE_FREE_CNT(_q_ptr, _q_depth) \
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(((_q_ptr)->consumer_index - (_q_ptr)->producer_index - 1) & \
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((_q_depth) - 1))
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#define BNA_QE_IN_USE_CNT(_q_ptr, _q_depth) \
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((((_q_ptr)->producer_index - (_q_ptr)->consumer_index)) & \
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(_q_depth - 1))
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#define BNA_Q_GET_CI(_q_ptr) ((_q_ptr)->q.consumer_index)
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#define BNA_Q_GET_PI(_q_ptr) ((_q_ptr)->q.producer_index)
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#define BNA_Q_PI_ADD(_q_ptr, _num) \
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(_q_ptr)->q.producer_index = \
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(((_q_ptr)->q.producer_index + (_num)) & \
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((_q_ptr)->q.q_depth - 1))
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2011-07-22 15:07:41 +07:00
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#define BNA_Q_CI_ADD(_q_ptr, _num) \
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2010-08-24 10:24:12 +07:00
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(_q_ptr)->q.consumer_index = \
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2011-07-22 15:07:41 +07:00
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(((_q_ptr)->q.consumer_index + (_num)) \
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2010-08-24 10:24:12 +07:00
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& ((_q_ptr)->q.q_depth - 1))
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#define BNA_Q_FREE_COUNT(_q_ptr) \
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(BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
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2011-07-22 15:07:41 +07:00
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#define BNA_Q_IN_USE_COUNT(_q_ptr) \
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2010-08-24 10:24:12 +07:00
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(BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
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#define BNA_LARGE_PKT_SIZE 1000
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#define BNA_UPDATE_PKT_CNT(_pkt, _len) \
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do { \
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if ((_len) > BNA_LARGE_PKT_SIZE) { \
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(_pkt)->large_pkt_cnt++; \
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} else { \
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(_pkt)->small_pkt_cnt++; \
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} \
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} while (0)
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
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#define call_rxf_stop_cbfn(rxf) \
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do { \
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2010-08-24 10:24:12 +07:00
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if ((rxf)->stop_cbfn) { \
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
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void (*cbfn)(struct bna_rx *); \
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struct bna_rx *cbarg; \
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cbfn = (rxf)->stop_cbfn; \
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cbarg = (rxf)->stop_cbarg; \
|
2010-08-24 10:24:12 +07:00
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|
(rxf)->stop_cbfn = NULL; \
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|
(rxf)->stop_cbarg = NULL; \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
cbfn(cbarg); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
#define call_rxf_start_cbfn(rxf) \
|
|
|
|
do { \
|
2010-08-24 10:24:12 +07:00
|
|
|
if ((rxf)->start_cbfn) { \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bna_rx *); \
|
|
|
|
struct bna_rx *cbarg; \
|
|
|
|
cbfn = (rxf)->start_cbfn; \
|
|
|
|
cbarg = (rxf)->start_cbarg; \
|
2010-08-24 10:24:12 +07:00
|
|
|
(rxf)->start_cbfn = NULL; \
|
|
|
|
(rxf)->start_cbarg = NULL; \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
cbfn(cbarg); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
#define call_rxf_cam_fltr_cbfn(rxf) \
|
|
|
|
do { \
|
2010-08-24 10:24:12 +07:00
|
|
|
if ((rxf)->cam_fltr_cbfn) { \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *); \
|
|
|
|
struct bnad *cbarg; \
|
|
|
|
cbfn = (rxf)->cam_fltr_cbfn; \
|
|
|
|
cbarg = (rxf)->cam_fltr_cbarg; \
|
2010-08-24 10:24:12 +07:00
|
|
|
(rxf)->cam_fltr_cbfn = NULL; \
|
|
|
|
(rxf)->cam_fltr_cbarg = NULL; \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
cbfn(cbarg, rxf->rx); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
#define call_rxf_pause_cbfn(rxf) \
|
|
|
|
do { \
|
2010-08-24 10:24:12 +07:00
|
|
|
if ((rxf)->oper_state_cbfn) { \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *); \
|
|
|
|
struct bnad *cbarg; \
|
|
|
|
cbfn = (rxf)->oper_state_cbfn; \
|
|
|
|
cbarg = (rxf)->oper_state_cbarg; \
|
2010-08-24 10:24:12 +07:00
|
|
|
(rxf)->oper_state_cbfn = NULL; \
|
|
|
|
(rxf)->oper_state_cbarg = NULL; \
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
cbfn(cbarg, rxf->rx); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
#define call_rxf_resume_cbfn(rxf) call_rxf_pause_cbfn(rxf)
|
2010-08-24 10:24:12 +07:00
|
|
|
|
|
|
|
#define is_xxx_enable(mode, bitmask, xxx) ((bitmask & xxx) && (mode & xxx))
|
|
|
|
|
|
|
|
#define is_xxx_disable(mode, bitmask, xxx) ((bitmask & xxx) && !(mode & xxx))
|
|
|
|
|
|
|
|
#define xxx_enable(mode, bitmask, xxx) \
|
|
|
|
do { \
|
|
|
|
bitmask |= xxx; \
|
|
|
|
mode |= xxx; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define xxx_disable(mode, bitmask, xxx) \
|
|
|
|
do { \
|
|
|
|
bitmask |= xxx; \
|
|
|
|
mode &= ~xxx; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define xxx_inactive(mode, bitmask, xxx) \
|
|
|
|
do { \
|
|
|
|
bitmask &= ~xxx; \
|
|
|
|
mode &= ~xxx; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define is_promisc_enable(mode, bitmask) \
|
|
|
|
is_xxx_enable(mode, bitmask, BNA_RXMODE_PROMISC)
|
|
|
|
|
|
|
|
#define is_promisc_disable(mode, bitmask) \
|
|
|
|
is_xxx_disable(mode, bitmask, BNA_RXMODE_PROMISC)
|
|
|
|
|
|
|
|
#define promisc_enable(mode, bitmask) \
|
|
|
|
xxx_enable(mode, bitmask, BNA_RXMODE_PROMISC)
|
|
|
|
|
|
|
|
#define promisc_disable(mode, bitmask) \
|
|
|
|
xxx_disable(mode, bitmask, BNA_RXMODE_PROMISC)
|
|
|
|
|
|
|
|
#define promisc_inactive(mode, bitmask) \
|
|
|
|
xxx_inactive(mode, bitmask, BNA_RXMODE_PROMISC)
|
|
|
|
|
|
|
|
#define is_default_enable(mode, bitmask) \
|
|
|
|
is_xxx_enable(mode, bitmask, BNA_RXMODE_DEFAULT)
|
|
|
|
|
|
|
|
#define is_default_disable(mode, bitmask) \
|
|
|
|
is_xxx_disable(mode, bitmask, BNA_RXMODE_DEFAULT)
|
|
|
|
|
|
|
|
#define default_enable(mode, bitmask) \
|
|
|
|
xxx_enable(mode, bitmask, BNA_RXMODE_DEFAULT)
|
|
|
|
|
|
|
|
#define default_disable(mode, bitmask) \
|
|
|
|
xxx_disable(mode, bitmask, BNA_RXMODE_DEFAULT)
|
|
|
|
|
|
|
|
#define default_inactive(mode, bitmask) \
|
|
|
|
xxx_inactive(mode, bitmask, BNA_RXMODE_DEFAULT)
|
|
|
|
|
|
|
|
#define is_allmulti_enable(mode, bitmask) \
|
|
|
|
is_xxx_enable(mode, bitmask, BNA_RXMODE_ALLMULTI)
|
|
|
|
|
|
|
|
#define is_allmulti_disable(mode, bitmask) \
|
|
|
|
is_xxx_disable(mode, bitmask, BNA_RXMODE_ALLMULTI)
|
|
|
|
|
|
|
|
#define allmulti_enable(mode, bitmask) \
|
|
|
|
xxx_enable(mode, bitmask, BNA_RXMODE_ALLMULTI)
|
|
|
|
|
|
|
|
#define allmulti_disable(mode, bitmask) \
|
|
|
|
xxx_disable(mode, bitmask, BNA_RXMODE_ALLMULTI)
|
|
|
|
|
|
|
|
#define allmulti_inactive(mode, bitmask) \
|
|
|
|
xxx_inactive(mode, bitmask, BNA_RXMODE_ALLMULTI)
|
|
|
|
|
|
|
|
#define GET_RXQS(rxp, q0, q1) do { \
|
|
|
|
switch ((rxp)->type) { \
|
|
|
|
case BNA_RXP_SINGLE: \
|
|
|
|
(q0) = rxp->rxq.single.only; \
|
|
|
|
(q1) = NULL; \
|
|
|
|
break; \
|
|
|
|
case BNA_RXP_SLR: \
|
|
|
|
(q0) = rxp->rxq.slr.large; \
|
|
|
|
(q1) = rxp->rxq.slr.small; \
|
|
|
|
break; \
|
|
|
|
case BNA_RXP_HDS: \
|
|
|
|
(q0) = rxp->rxq.hds.data; \
|
|
|
|
(q1) = rxp->rxq.hds.hdr; \
|
|
|
|
break; \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
#define bna_tx_rid_mask(_bna) ((_bna)->tx_mod.rid_mask)
|
|
|
|
|
|
|
|
#define bna_rx_rid_mask(_bna) ((_bna)->rx_mod.rid_mask)
|
|
|
|
|
|
|
|
#define bna_tx_from_rid(_bna, _rid, _tx) \
|
|
|
|
do { \
|
|
|
|
struct bna_tx_mod *__tx_mod = &(_bna)->tx_mod; \
|
|
|
|
struct bna_tx *__tx; \
|
|
|
|
struct list_head *qe; \
|
|
|
|
_tx = NULL; \
|
|
|
|
list_for_each(qe, &__tx_mod->tx_active_q) { \
|
|
|
|
__tx = (struct bna_tx *)qe; \
|
|
|
|
if (__tx->rid == (_rid)) { \
|
|
|
|
(_tx) = __tx; \
|
|
|
|
break; \
|
|
|
|
} \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define bna_rx_from_rid(_bna, _rid, _rx) \
|
|
|
|
do { \
|
|
|
|
struct bna_rx_mod *__rx_mod = &(_bna)->rx_mod; \
|
|
|
|
struct bna_rx *__rx; \
|
|
|
|
struct list_head *qe; \
|
|
|
|
_rx = NULL; \
|
|
|
|
list_for_each(qe, &__rx_mod->rx_active_q) { \
|
|
|
|
__rx = (struct bna_rx *)qe; \
|
|
|
|
if (__rx->rid == (_rid)) { \
|
|
|
|
(_rx) = __rx; \
|
|
|
|
break; \
|
|
|
|
} \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
2013-12-18 08:07:33 +07:00
|
|
|
#define bna_mcam_mod_free_q(_bna) (&(_bna)->mcam_mod.free_q)
|
|
|
|
|
|
|
|
#define bna_mcam_mod_del_q(_bna) (&(_bna)->mcam_mod.del_q)
|
|
|
|
|
|
|
|
#define bna_ucam_mod_free_q(_bna) (&(_bna)->ucam_mod.free_q)
|
|
|
|
|
|
|
|
#define bna_ucam_mod_del_q(_bna) (&(_bna)->ucam_mod.del_q)
|
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* Inline functions */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
|
|
|
|
static inline struct bna_mac *bna_mac_find(struct list_head *q, u8 *addr)
|
|
|
|
{
|
|
|
|
struct bna_mac *mac = NULL;
|
|
|
|
struct list_head *qe;
|
|
|
|
list_for_each(qe, q) {
|
|
|
|
if (BNA_MAC_IS_EQUAL(((struct bna_mac *)qe)->addr, addr)) {
|
|
|
|
mac = (struct bna_mac *)qe;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return mac;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define bna_attr(_bna) (&(_bna)->ioceth.attr)
|
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* Function prototypes */
|
2010-08-24 10:24:12 +07:00
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* BNA */
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
/* FW response handlers */
|
|
|
|
void bna_bfi_stats_clr_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr);
|
|
|
|
|
2010-08-24 10:24:12 +07:00
|
|
|
/* APIs for BNAD */
|
|
|
|
void bna_res_req(struct bna_res_info *res_info);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void bna_mod_res_req(struct bna *bna, struct bna_res_info *res_info);
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_init(struct bna *bna, struct bnad *bnad,
|
|
|
|
struct bfa_pcidev *pcidev,
|
|
|
|
struct bna_res_info *res_info);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void bna_mod_init(struct bna *bna, struct bna_res_info *res_info);
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_uninit(struct bna *bna);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
int bna_num_txq_set(struct bna *bna, int num_txq);
|
|
|
|
int bna_num_rxp_set(struct bna *bna, int num_rxp);
|
|
|
|
void bna_hw_stats_get(struct bna *bna);
|
2010-08-24 10:24:12 +07:00
|
|
|
|
|
|
|
/* APIs for RxF */
|
2013-12-18 08:07:33 +07:00
|
|
|
struct bna_mac *bna_cam_mod_mac_get(struct list_head *head);
|
|
|
|
void bna_cam_mod_mac_put(struct list_head *tail, struct bna_mac *mac);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
struct bna_mcam_handle *bna_mcam_mod_handle_get(struct bna_mcam_mod *mod);
|
|
|
|
void bna_mcam_mod_handle_put(struct bna_mcam_mod *mcam_mod,
|
|
|
|
struct bna_mcam_handle *handle);
|
2010-08-24 10:24:12 +07:00
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* MBOX */
|
2010-08-24 10:24:12 +07:00
|
|
|
|
|
|
|
/* API for BNAD */
|
2011-08-08 23:21:40 +07:00
|
|
|
void bna_mbox_handler(struct bna *bna, u32 intr_status);
|
2010-08-24 10:24:12 +07:00
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* ETHPORT */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
|
|
|
|
/* Callbacks for RX */
|
|
|
|
void bna_ethport_cb_rx_started(struct bna_ethport *ethport);
|
|
|
|
void bna_ethport_cb_rx_stopped(struct bna_ethport *ethport);
|
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* TX MODULE AND TX */
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
/* FW response handelrs */
|
|
|
|
void bna_bfi_tx_enet_start_rsp(struct bna_tx *tx,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
|
|
|
void bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
|
|
|
void bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod);
|
2010-08-24 10:24:12 +07:00
|
|
|
|
|
|
|
/* APIs for BNA */
|
|
|
|
void bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
|
|
|
|
struct bna_res_info *res_info);
|
|
|
|
void bna_tx_mod_uninit(struct bna_tx_mod *tx_mod);
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
/* APIs for ENET */
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type);
|
|
|
|
void bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type);
|
|
|
|
void bna_tx_mod_fail(struct bna_tx_mod *tx_mod);
|
|
|
|
|
|
|
|
/* APIs for BNAD */
|
|
|
|
void bna_tx_res_req(int num_txq, int txq_depth,
|
|
|
|
struct bna_res_info *res_info);
|
|
|
|
struct bna_tx *bna_tx_create(struct bna *bna, struct bnad *bnad,
|
|
|
|
struct bna_tx_config *tx_cfg,
|
2011-09-16 18:09:51 +07:00
|
|
|
const struct bna_tx_event_cbfn *tx_cbfn,
|
2010-08-24 10:24:12 +07:00
|
|
|
struct bna_res_info *res_info, void *priv);
|
|
|
|
void bna_tx_destroy(struct bna_tx *tx);
|
|
|
|
void bna_tx_enable(struct bna_tx *tx);
|
|
|
|
void bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(void *, struct bna_tx *));
|
|
|
|
void bna_tx_cleanup_complete(struct bna_tx *tx);
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo);
|
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* RX MODULE, RX, RXF */
|
2010-08-24 10:24:12 +07:00
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
/* FW response handlers */
|
|
|
|
void bna_bfi_rx_enet_start_rsp(struct bna_rx *rx,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
|
|
|
void bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
|
|
|
void bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr);
|
|
|
|
void bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
2013-05-20 17:08:02 +07:00
|
|
|
void bna_bfi_rxf_ucast_set_rsp(struct bna_rxf *rxf,
|
|
|
|
struct bfi_msgq_mhdr *msghdr);
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
|
2010-08-24 10:24:12 +07:00
|
|
|
/* APIs for BNA */
|
|
|
|
void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
|
|
|
|
struct bna_res_info *res_info);
|
|
|
|
void bna_rx_mod_uninit(struct bna_rx_mod *rx_mod);
|
|
|
|
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
/* APIs for ENET */
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type);
|
|
|
|
void bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type);
|
|
|
|
void bna_rx_mod_fail(struct bna_rx_mod *rx_mod);
|
|
|
|
|
|
|
|
/* APIs for BNAD */
|
|
|
|
void bna_rx_res_req(struct bna_rx_config *rx_config,
|
|
|
|
struct bna_res_info *res_info);
|
|
|
|
struct bna_rx *bna_rx_create(struct bna *bna, struct bnad *bnad,
|
|
|
|
struct bna_rx_config *rx_cfg,
|
2011-09-16 18:09:51 +07:00
|
|
|
const struct bna_rx_event_cbfn *rx_cbfn,
|
2010-08-24 10:24:12 +07:00
|
|
|
struct bna_res_info *res_info, void *priv);
|
|
|
|
void bna_rx_destroy(struct bna_rx *rx);
|
|
|
|
void bna_rx_enable(struct bna_rx *rx);
|
|
|
|
void bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(void *, struct bna_rx *));
|
|
|
|
void bna_rx_cleanup_complete(struct bna_rx *rx);
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo);
|
2010-10-05 22:46:05 +07:00
|
|
|
void bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX]);
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_rx_dim_update(struct bna_ccb *ccb);
|
|
|
|
enum bna_cb_status
|
|
|
|
bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
|
|
|
enum bna_cb_status
|
|
|
|
bna_rx_ucast_add(struct bna_rx *rx, u8* ucmac,
|
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
|
|
|
enum bna_cb_status
|
|
|
|
bna_rx_ucast_del(struct bna_rx *rx, u8 *ucmac,
|
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
2010-08-24 10:24:12 +07:00
|
|
|
enum bna_cb_status
|
2013-12-18 08:07:34 +07:00
|
|
|
bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist,
|
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
|
|
|
enum bna_cb_status
|
2010-08-24 10:24:12 +07:00
|
|
|
bna_rx_mcast_add(struct bna_rx *rx, u8 *mcmac,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
2010-08-24 10:24:12 +07:00
|
|
|
enum bna_cb_status
|
|
|
|
bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
2013-12-18 08:07:34 +07:00
|
|
|
void
|
|
|
|
bna_rx_mcast_delall(struct bna_rx *rx,
|
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
2010-08-24 10:24:12 +07:00
|
|
|
enum bna_cb_status
|
|
|
|
bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode rxmode,
|
|
|
|
enum bna_rxmode bitmask,
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
void (*cbfn)(struct bnad *, struct bna_rx *));
|
2010-08-24 10:24:12 +07:00
|
|
|
void bna_rx_vlan_add(struct bna_rx *rx, int vlan_id);
|
|
|
|
void bna_rx_vlan_del(struct bna_rx *rx, int vlan_id);
|
|
|
|
void bna_rx_vlanfilter_enable(struct bna_rx *rx);
|
2013-12-18 08:07:34 +07:00
|
|
|
void bna_rx_vlan_strip_enable(struct bna_rx *rx);
|
|
|
|
void bna_rx_vlan_strip_disable(struct bna_rx *rx);
|
2012-07-10 17:56:59 +07:00
|
|
|
/* ENET */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
|
|
|
|
/* API for RX */
|
|
|
|
int bna_enet_mtu_get(struct bna_enet *enet);
|
|
|
|
|
|
|
|
/* Callbacks for TX, RX */
|
|
|
|
void bna_enet_cb_tx_stopped(struct bna_enet *enet);
|
|
|
|
void bna_enet_cb_rx_stopped(struct bna_enet *enet);
|
|
|
|
|
|
|
|
/* API for BNAD */
|
|
|
|
void bna_enet_enable(struct bna_enet *enet);
|
|
|
|
void bna_enet_disable(struct bna_enet *enet, enum bna_cleanup_type type,
|
|
|
|
void (*cbfn)(void *));
|
|
|
|
void bna_enet_pause_config(struct bna_enet *enet,
|
|
|
|
struct bna_pause_config *pause_config,
|
|
|
|
void (*cbfn)(struct bnad *));
|
|
|
|
void bna_enet_mtu_set(struct bna_enet *enet, int mtu,
|
|
|
|
void (*cbfn)(struct bnad *));
|
|
|
|
void bna_enet_perm_mac_get(struct bna_enet *enet, mac_t *mac);
|
|
|
|
|
2012-07-10 17:56:59 +07:00
|
|
|
/* IOCETH */
|
bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
|
|
|
|
|
|
|
/* APIs for BNAD */
|
|
|
|
void bna_ioceth_enable(struct bna_ioceth *ioceth);
|
|
|
|
void bna_ioceth_disable(struct bna_ioceth *ioceth,
|
|
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enum bna_cleanup_type type);
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2010-08-24 10:24:12 +07:00
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2012-07-10 17:56:59 +07:00
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/* BNAD */
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2010-08-24 10:24:12 +07:00
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bna: ENET and Tx Rx Redesign Enablement
Change details:
This patch contains additional structure and function definition changes
that are required to enable the new msgq/enet/txrx redesign introduced
by the previous 4 patches.
- structure and function definition changes to header files as a result
of Ethport, Enet, IOCEth, Tx, Rx redesign.
- ethtool changes to use new enet function and definitions
- Set number of Tx and Rx queues bassed on underlying hardware. Define
separate macros for maximum and supported numbers of Tx and Rx queues
based on underlying hardware. Take VLAN header into account for MTU
calculation. Default to INTx mode when pci_enable_msix() fails. Set a
bit in Rx poll routine, check and wait for that bit to be cleared in
the cleanup routine before proceeding.
- The TX and Rx coalesce settings are programmed in steps of 5 us. The value
that are not divisible by 5 are rounded to the next lower number. This was
causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
When creating Rx and Tx object, we are currently assigning the default
values of Rx and Tx coalescing_timeo. If these values are changed in the
driver to a different value, the change is lost during such operations as
MTU change. In order to avoid that, pass the configured value of
coalescing_timeo before Rx and Tx object creation. Fix
bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
- Reorg uninitialization path in case of pci_probe failure.
- Hardware clock setup changes to pass asic generation, port modes and
asic mode as part firmware boot parameters to firmware.
- FW mailbox interface changes to defined asic specific mailbox interfaces.
h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
up mailbox definitions and usage for new and old HW. Eliminated usage of
ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
host offsets for CPE/RME queue registers.
- Implement polling mechanism for FW ready to have poll mechanism replaces
the current interrupt based FW READY method. The timer based poll routine
in IOC will query the ioc_fwstate register to see if there is a state
change in FW, and sends the READY event. Removed infrastructure needed to
support mbox READY event from fw as well as IOC code.
- Move FW init to HW init. Handle the case where PCI mapping goes away when
IOCPF state machine is waiting for semaphore.
- Add IOC mbox call back to client indicating that the command is sent.
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-08-08 23:21:39 +07:00
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/* Callbacks for ENET */
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void bnad_cb_ethport_link_status(struct bnad *bnad,
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enum bna_link_status status);
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/* Callbacks for IOCETH */
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void bnad_cb_ioceth_ready(struct bnad *bnad);
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void bnad_cb_ioceth_failed(struct bnad *bnad);
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void bnad_cb_ioceth_disabled(struct bnad *bnad);
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void bnad_cb_mbox_intr_enable(struct bnad *bnad);
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void bnad_cb_mbox_intr_disable(struct bnad *bnad);
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2010-08-24 10:24:12 +07:00
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/* Callbacks for BNA */
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void bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
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struct bna_stats *stats);
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#endif /* __BNA_H__ */
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