2005-04-17 05:20:36 +07:00
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/*
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* PowerPC64 Segment Translation Support.
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*
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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*
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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2010-07-12 11:36:09 +07:00
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#include <linux/memblock.h>
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2008-02-14 07:56:49 +07:00
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2005-04-17 05:20:36 +07:00
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/paca.h>
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#include <asm/cputable.h>
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2008-02-14 07:56:49 +07:00
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#include <asm/prom.h>
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2005-07-28 01:44:19 +07:00
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#include <asm/abs_addr.h>
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2005-11-10 09:37:51 +07:00
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#include <asm/firmware.h>
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2007-11-19 13:44:05 +07:00
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#include <asm/iseries/hv_call.h>
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2005-04-17 05:20:36 +07:00
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2005-05-06 06:15:13 +07:00
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struct stab_entry {
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unsigned long esid_data;
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unsigned long vsid_data;
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};
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2005-04-17 05:20:36 +07:00
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#define NR_STAB_CACHE_ENTRIES 8
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2008-05-08 11:27:07 +07:00
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static DEFINE_PER_CPU(long, stab_cache_ptr);
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2009-06-24 13:13:45 +07:00
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static DEFINE_PER_CPU(long [NR_STAB_CACHE_ENTRIES], stab_cache);
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2005-04-17 05:20:36 +07:00
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/*
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* Create a segment table entry for the given esid/vsid pair.
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*/
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static int make_ste(unsigned long stab, unsigned long esid, unsigned long vsid)
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{
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unsigned long esid_data, vsid_data;
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unsigned long entry, group, old_esid, castout_entry, i;
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unsigned int global_entry;
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struct stab_entry *ste, *castout_ste;
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2005-12-05 23:24:33 +07:00
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unsigned long kernel_segment = (esid << SID_SHIFT) >= PAGE_OFFSET;
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2005-04-17 05:20:36 +07:00
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vsid_data = vsid << STE_VSID_SHIFT;
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esid_data = esid << SID_SHIFT | STE_ESID_KP | STE_ESID_V;
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if (! kernel_segment)
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esid_data |= STE_ESID_KS;
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/* Search the primary group first. */
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global_entry = (esid & 0x1f) << 3;
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ste = (struct stab_entry *)(stab | ((esid & 0x1f) << 7));
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/* Find an empty entry, if one exists. */
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for (group = 0; group < 2; group++) {
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for (entry = 0; entry < 8; entry++, ste++) {
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if (!(ste->esid_data & STE_ESID_V)) {
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ste->vsid_data = vsid_data;
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2007-07-10 11:49:09 +07:00
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eieio();
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2005-04-17 05:20:36 +07:00
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ste->esid_data = esid_data;
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return (global_entry | entry);
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}
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}
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/* Now search the secondary group. */
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global_entry = ((~esid) & 0x1f) << 3;
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ste = (struct stab_entry *)(stab | (((~esid) & 0x1f) << 7));
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}
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/*
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* Could not find empty entry, pick one with a round robin selection.
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* Search all entries in the two groups.
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*/
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castout_entry = get_paca()->stab_rr;
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for (i = 0; i < 16; i++) {
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if (castout_entry < 8) {
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global_entry = (esid & 0x1f) << 3;
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ste = (struct stab_entry *)(stab | ((esid & 0x1f) << 7));
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castout_ste = ste + castout_entry;
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} else {
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global_entry = ((~esid) & 0x1f) << 3;
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ste = (struct stab_entry *)(stab | (((~esid) & 0x1f) << 7));
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castout_ste = ste + (castout_entry - 8);
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}
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/* Dont cast out the first kernel segment */
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2005-12-05 23:24:33 +07:00
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if ((castout_ste->esid_data & ESID_MASK) != PAGE_OFFSET)
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2005-04-17 05:20:36 +07:00
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break;
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castout_entry = (castout_entry + 1) & 0xf;
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}
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get_paca()->stab_rr = (castout_entry + 1) & 0xf;
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/* Modify the old entry to the new value. */
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/* Force previous translations to complete. DRENG */
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asm volatile("isync" : : : "memory");
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old_esid = castout_ste->esid_data >> SID_SHIFT;
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castout_ste->esid_data = 0; /* Invalidate old entry */
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asm volatile("sync" : : : "memory"); /* Order update */
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castout_ste->vsid_data = vsid_data;
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2007-07-10 11:49:09 +07:00
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eieio(); /* Order update */
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2005-04-17 05:20:36 +07:00
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castout_ste->esid_data = esid_data;
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asm volatile("slbie %0" : : "r" (old_esid << SID_SHIFT));
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/* Ensure completion of slbie */
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asm volatile("sync" : : : "memory");
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return (global_entry | (castout_entry & 0x7));
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}
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/*
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* Allocate a segment table entry for the given ea and mm
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*/
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static int __ste_allocate(unsigned long ea, struct mm_struct *mm)
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{
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unsigned long vsid;
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unsigned char stab_entry;
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unsigned long offset;
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/* Kernel or user address? */
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2005-12-04 14:39:15 +07:00
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if (is_kernel_addr(ea)) {
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2007-10-11 17:37:10 +07:00
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vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
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2005-04-17 05:20:36 +07:00
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} else {
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if ((ea >= TASK_SIZE_USER64) || (! mm))
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return 1;
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2007-10-11 17:37:10 +07:00
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vsid = get_vsid(mm->context.id, ea, MMU_SEGSIZE_256M);
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2005-04-17 05:20:36 +07:00
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}
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stab_entry = make_ste(get_paca()->stab_addr, GET_ESID(ea), vsid);
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2005-12-04 14:39:15 +07:00
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if (!is_kernel_addr(ea)) {
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2005-04-17 05:20:36 +07:00
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offset = __get_cpu_var(stab_cache_ptr);
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if (offset < NR_STAB_CACHE_ENTRIES)
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__get_cpu_var(stab_cache[offset++]) = stab_entry;
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else
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offset = NR_STAB_CACHE_ENTRIES+1;
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__get_cpu_var(stab_cache_ptr) = offset;
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/* Order update */
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asm volatile("sync":::"memory");
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}
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return 0;
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}
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int ste_allocate(unsigned long ea)
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{
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return __ste_allocate(ea, current->mm);
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}
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/*
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* Do the segment table work for a context switch: flush all user
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* entries from the table, then preload some probably useful entries
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* for the new task
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*/
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void switch_stab(struct task_struct *tsk, struct mm_struct *mm)
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{
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struct stab_entry *stab = (struct stab_entry *) get_paca()->stab_addr;
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struct stab_entry *ste;
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powerpc: Allow perf_counters to access user memory at interrupt time
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/server processors, which use an MMU
hash table. 32-bit processors are already able to access user memory
at interrupt time. Since we don't soft-disable on 32-bit, we avoid
the possibility of reentering hash_page or the TLB miss handlers,
since they run with interrupts disabled.
On 64-bit processors, an SLB miss interrupt on a user address will
update the slb_cache and slb_cache_ptr fields in the paca. This is
OK except in the case where a PMU interrupt occurs in switch_slb,
which also accesses those fields. To prevent this, we hard-disable
interrupts in switch_slb. Interrupts are already soft-disabled at
this point, and will get hard-enabled when they get soft-enabled
later.
This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice,
and to make sure that it clears the slb_cache_ptr when called from
other callers than switch_slb, the existing routine is renamed to
__slb_flush_and_rebolt, which is called by switch_slb and the new
version of slb_flush_and_rebolt.
Similarly, switch_stab (used on POWER3 and RS64 processors) gets a
hard_irq_disable() to protect the per-cpu variables used there and
in ste_allocate.
If a MMU hashtable miss interrupt occurs, normally we would call
hash_page to look up the Linux PTE for the address and create a HPTE.
However, hash_page is fairly complex and takes some locks, so to
avoid the possibility of deadlock, we check the preemption count
to see if we are in a (pseudo-)NMI handler, and if so, we don't call
hash_page but instead treat it like a bad access that will get
reported up through the exception table mechanism. An interrupt
whose handler runs even though the interrupt occurred when
soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI
handler, which should use nmi_enter()/nmi_exit() rather than
irq_enter()/irq_exit().
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 12:17:54 +07:00
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unsigned long offset;
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2005-04-17 05:20:36 +07:00
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unsigned long pc = KSTK_EIP(tsk);
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unsigned long stack = KSTK_ESP(tsk);
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unsigned long unmapped_base;
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/* Force previous translations to complete. DRENG */
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asm volatile("isync" : : : "memory");
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powerpc: Allow perf_counters to access user memory at interrupt time
This provides a mechanism to allow the perf_counters code to access
user memory in a PMU interrupt routine. Such an access can cause
various kinds of interrupt: SLB miss, MMU hash table miss, segment
table miss, or TLB miss, depending on the processor. This commit
only deals with 64-bit classic/server processors, which use an MMU
hash table. 32-bit processors are already able to access user memory
at interrupt time. Since we don't soft-disable on 32-bit, we avoid
the possibility of reentering hash_page or the TLB miss handlers,
since they run with interrupts disabled.
On 64-bit processors, an SLB miss interrupt on a user address will
update the slb_cache and slb_cache_ptr fields in the paca. This is
OK except in the case where a PMU interrupt occurs in switch_slb,
which also accesses those fields. To prevent this, we hard-disable
interrupts in switch_slb. Interrupts are already soft-disabled at
this point, and will get hard-enabled when they get soft-enabled
later.
This also reworks slb_flush_and_rebolt: to avoid hard-disabling twice,
and to make sure that it clears the slb_cache_ptr when called from
other callers than switch_slb, the existing routine is renamed to
__slb_flush_and_rebolt, which is called by switch_slb and the new
version of slb_flush_and_rebolt.
Similarly, switch_stab (used on POWER3 and RS64 processors) gets a
hard_irq_disable() to protect the per-cpu variables used there and
in ste_allocate.
If a MMU hashtable miss interrupt occurs, normally we would call
hash_page to look up the Linux PTE for the address and create a HPTE.
However, hash_page is fairly complex and takes some locks, so to
avoid the possibility of deadlock, we check the preemption count
to see if we are in a (pseudo-)NMI handler, and if so, we don't call
hash_page but instead treat it like a bad access that will get
reported up through the exception table mechanism. An interrupt
whose handler runs even though the interrupt occurred when
soft-disabled (such as the PMU interrupt) is considered a pseudo-NMI
handler, which should use nmi_enter()/nmi_exit() rather than
irq_enter()/irq_exit().
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 12:17:54 +07:00
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/*
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* We need interrupts hard-disabled here, not just soft-disabled,
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* so that a PMU interrupt can't occur, which might try to access
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* user memory (to get a stack trace) and possible cause an STAB miss
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* which would update the stab_cache/stab_cache_ptr per-cpu variables.
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*/
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hard_irq_disable();
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offset = __get_cpu_var(stab_cache_ptr);
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2005-04-17 05:20:36 +07:00
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if (offset <= NR_STAB_CACHE_ENTRIES) {
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int i;
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for (i = 0; i < offset; i++) {
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ste = stab + __get_cpu_var(stab_cache[i]);
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ste->esid_data = 0; /* invalidate entry */
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}
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} else {
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unsigned long entry;
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/* Invalidate all entries. */
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ste = stab;
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/* Never flush the first entry. */
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ste += 1;
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for (entry = 1;
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2005-11-07 07:06:55 +07:00
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entry < (HW_PAGE_SIZE / sizeof(struct stab_entry));
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2005-04-17 05:20:36 +07:00
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entry++, ste++) {
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unsigned long ea;
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ea = ste->esid_data & ESID_MASK;
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2005-12-04 14:39:15 +07:00
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if (!is_kernel_addr(ea)) {
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2005-04-17 05:20:36 +07:00
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ste->esid_data = 0;
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}
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}
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}
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asm volatile("sync; slbia; sync":::"memory");
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__get_cpu_var(stab_cache_ptr) = 0;
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/* Now preload some entries for the new task */
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if (test_tsk_thread_flag(tsk, TIF_32BIT))
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unmapped_base = TASK_UNMAPPED_BASE_USER32;
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else
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unmapped_base = TASK_UNMAPPED_BASE_USER64;
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__ste_allocate(pc, mm);
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if (GET_ESID(pc) == GET_ESID(stack))
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return;
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__ste_allocate(stack, mm);
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if ((GET_ESID(pc) == GET_ESID(unmapped_base))
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|| (GET_ESID(stack) == GET_ESID(unmapped_base)))
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return;
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__ste_allocate(unmapped_base, mm);
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/* Order update */
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asm volatile("sync" : : : "memory");
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}
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2005-07-28 01:44:19 +07:00
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/*
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* Allocate segment tables for secondary CPUs. These must all go in
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* the first (bolted) segment, so that do_stab_bolted won't get a
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* recursive segment miss on the segment table itself.
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*/
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2007-05-07 12:58:28 +07:00
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void __init stabs_alloc(void)
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2005-07-28 01:44:19 +07:00
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{
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int cpu;
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if (cpu_has_feature(CPU_FTR_SLB))
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return;
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2006-03-29 05:50:51 +07:00
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for_each_possible_cpu(cpu) {
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2005-07-28 01:44:19 +07:00
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unsigned long newstab;
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if (cpu == 0)
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continue; /* stab for CPU 0 is statically allocated */
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2010-07-12 11:36:09 +07:00
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newstab = memblock_alloc_base(HW_PAGE_SIZE, HW_PAGE_SIZE,
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2005-11-07 07:06:55 +07:00
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1<<SID_SHIFT);
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2005-12-05 23:24:33 +07:00
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newstab = (unsigned long)__va(newstab);
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2005-07-28 01:44:19 +07:00
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2005-11-07 07:06:55 +07:00
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memset((void *)newstab, 0, HW_PAGE_SIZE);
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2005-07-28 01:44:19 +07:00
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paca[cpu].stab_addr = newstab;
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paca[cpu].stab_real = virt_to_abs(newstab);
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2009-01-06 21:26:03 +07:00
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printk(KERN_INFO "Segment table for CPU %d at 0x%llx "
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"virtual, 0x%llx absolute\n",
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2005-11-07 07:06:55 +07:00
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cpu, paca[cpu].stab_addr, paca[cpu].stab_real);
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2005-07-28 01:44:19 +07:00
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}
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}
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2005-04-17 05:20:36 +07:00
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/*
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* Build an entry for the base kernel segment and put it into
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* the segment table or SLB. All other segment table or SLB
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* entries are faulted in.
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*/
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void stab_initialize(unsigned long stab)
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{
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2007-10-11 17:37:10 +07:00
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unsigned long vsid = get_kernel_vsid(PAGE_OFFSET, MMU_SEGSIZE_256M);
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2005-11-10 09:37:51 +07:00
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unsigned long stabreal;
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2005-04-17 05:20:36 +07:00
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2005-11-07 07:06:55 +07:00
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asm volatile("isync; slbia; isync":::"memory");
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2005-12-05 23:24:33 +07:00
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make_ste(stab, GET_ESID(PAGE_OFFSET), vsid);
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2005-04-17 05:20:36 +07:00
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2005-11-07 07:06:55 +07:00
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/* Order update */
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asm volatile("sync":::"memory");
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2005-11-10 09:37:51 +07:00
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/* Set ASR */
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stabreal = get_paca()->stab_real | 0x1ul;
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#ifdef CONFIG_PPC_ISERIES
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if (firmware_has_feature(FW_FEATURE_ISERIES)) {
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HvCall1(HvCallBaseSetASR, stabreal);
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return;
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}
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#endif /* CONFIG_PPC_ISERIES */
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2005-11-30 03:04:17 +07:00
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2005-11-10 09:37:51 +07:00
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mtspr(SPRN_ASR, stabreal);
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2005-04-17 05:20:36 +07:00
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}
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