mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 21:56:40 +07:00
328 lines
9.0 KiB
C
328 lines
9.0 KiB
C
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/*
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* FSI hub master driver
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*
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* Copyright (C) IBM Corporation 2016
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/fsi.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include "fsi-master.h"
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/* Control Registers */
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#define FSI_MMODE 0x0 /* R/W: mode */
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#define FSI_MDLYR 0x4 /* R/W: delay */
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#define FSI_MCRSP 0x8 /* R/W: clock rate */
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#define FSI_MENP0 0x10 /* R/W: enable */
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#define FSI_MLEVP0 0x18 /* R: plug detect */
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#define FSI_MSENP0 0x18 /* S: Set enable */
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#define FSI_MCENP0 0x20 /* C: Clear enable */
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#define FSI_MAEB 0x70 /* R: Error address */
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#define FSI_MVER 0x74 /* R: master version/type */
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#define FSI_MRESP0 0xd0 /* W: Port reset */
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#define FSI_MESRB0 0x1d0 /* R: Master error status */
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#define FSI_MRESB0 0x1d0 /* W: Reset bridge */
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#define FSI_MECTRL 0x2e0 /* W: Error control */
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/* MMODE: Mode control */
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#define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */
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#define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */
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#define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */
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#define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */
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/* MSB=1, LSB=0 is 0.8 ms */
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/* MSB=0, LSB=1 is 0.9 ms */
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#define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */
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#define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */
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#define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */
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#define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */
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/* MRESB: Reset brindge */
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#define FSI_MRESB_RST_GEN 0x80000000 /* General reset */
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#define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */
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/* MRESB: Reset port */
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#define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
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#define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */
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#define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */
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#define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */
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#define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */
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/* MECTRL: Error control */
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#define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */
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/* master 0 in error */
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#define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */
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#define FSI_ENGID_HUB_MASTER 0x1c
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#define FSI_HUB_LINK_OFFSET 0x80000
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#define FSI_HUB_LINK_SIZE 0x80000
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#define FSI_HUB_MASTER_MAX_LINKS 8
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#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */
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/*
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* FSI hub master support
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*
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* A hub master increases the number of potential target devices that the
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* primary FSI master can access. For each link a primary master supports,
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* each of those links can in turn be chained to a hub master with multiple
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* links of its own.
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*
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* The hub is controlled by a set of control registers exposed as a regular fsi
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* device (the hub->upstream device), and provides access to the downstream FSI
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* bus as through an address range on the slave itself (->addr and ->size).
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*
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* [This differs from "cascaded" masters, which expose the entire downstream
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* bus entirely through the fsi device address range, and so have a smaller
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* accessible address space.]
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*/
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struct fsi_master_hub {
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struct fsi_master master;
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struct fsi_device *upstream;
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uint32_t addr, size; /* slave-relative addr of */
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/* master address space */
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};
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#define to_fsi_master_hub(m) container_of(m, struct fsi_master_hub, master)
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static int hub_master_read(struct fsi_master *master, int link,
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uint8_t id, uint32_t addr, void *val, size_t size)
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{
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struct fsi_master_hub *hub = to_fsi_master_hub(master);
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if (id != 0)
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return -EINVAL;
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addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
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return fsi_slave_read(hub->upstream->slave, addr, val, size);
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}
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static int hub_master_write(struct fsi_master *master, int link,
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uint8_t id, uint32_t addr, const void *val, size_t size)
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{
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struct fsi_master_hub *hub = to_fsi_master_hub(master);
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if (id != 0)
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return -EINVAL;
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addr += hub->addr + (link * FSI_HUB_LINK_SIZE);
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return fsi_slave_write(hub->upstream->slave, addr, val, size);
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}
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static int hub_master_break(struct fsi_master *master, int link)
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{
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uint32_t addr, cmd;
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addr = 0x4;
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cmd = cpu_to_be32(0xc0de0000);
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return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd));
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}
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static int hub_master_link_enable(struct fsi_master *master, int link)
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{
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struct fsi_master_hub *hub = to_fsi_master_hub(master);
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int idx, bit;
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__be32 reg;
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int rc;
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idx = link / 32;
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bit = link % 32;
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reg = cpu_to_be32(0x80000000 >> bit);
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rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), ®, 4);
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mdelay(FSI_LINK_ENABLE_SETUP_TIME);
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fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), ®, 4);
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return rc;
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}
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static void hub_master_release(struct device *dev)
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{
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struct fsi_master_hub *hub = to_fsi_master_hub(dev_to_fsi_master(dev));
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kfree(hub);
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}
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/* mmode encoders */
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static inline u32 fsi_mmode_crs0(u32 x)
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{
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return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
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}
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static inline u32 fsi_mmode_crs1(u32 x)
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{
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return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
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}
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static int hub_master_init(struct fsi_master_hub *hub)
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{
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struct fsi_device *dev = hub->upstream;
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__be32 reg;
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int rc;
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
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rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg));
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if (rc)
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return rc;
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/* Initialize the MFSI (hub master) engine */
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
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rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
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rc = fsi_device_write(dev, FSI_MECTRL, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC
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| fsi_mmode_crs0(1) | fsi_mmode_crs1(1)
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| FSI_MMODE_P8_TO_LSB);
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rc = fsi_device_write(dev, FSI_MMODE, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = cpu_to_be32(0xffff0000);
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rc = fsi_device_write(dev, FSI_MDLYR, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = ~0;
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rc = fsi_device_write(dev, FSI_MSENP0, ®, sizeof(reg));
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if (rc)
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return rc;
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/* Leave enabled long enough for master logic to set up */
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mdelay(FSI_LINK_ENABLE_SETUP_TIME);
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rc = fsi_device_write(dev, FSI_MCENP0, ®, sizeof(reg));
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if (rc)
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return rc;
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rc = fsi_device_read(dev, FSI_MAEB, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
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rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg));
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if (rc)
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return rc;
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rc = fsi_device_read(dev, FSI_MLEVP0, ®, sizeof(reg));
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if (rc)
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return rc;
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/* Reset the master bridge */
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reg = cpu_to_be32(FSI_MRESB_RST_GEN);
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rc = fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg));
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if (rc)
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return rc;
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reg = cpu_to_be32(FSI_MRESB_RST_ERR);
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return fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg));
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}
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static int hub_master_probe(struct device *dev)
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{
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struct fsi_device *fsi_dev = to_fsi_dev(dev);
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struct fsi_master_hub *hub;
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uint32_t reg, links;
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__be32 __reg;
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int rc;
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rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg));
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if (rc)
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return rc;
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reg = be32_to_cpu(__reg);
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links = (reg >> 8) & 0xff;
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dev_info(dev, "hub version %08x (%d links)\n", reg, links);
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rc = fsi_slave_claim_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
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FSI_HUB_LINK_SIZE * links);
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if (rc) {
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dev_err(dev, "can't claim slave address range for links");
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return rc;
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}
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hub = kzalloc(sizeof(*hub), GFP_KERNEL);
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if (!hub) {
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rc = -ENOMEM;
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goto err_release;
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}
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hub->addr = FSI_HUB_LINK_OFFSET;
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hub->size = FSI_HUB_LINK_SIZE * links;
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hub->upstream = fsi_dev;
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hub->master.dev.parent = dev;
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hub->master.dev.release = hub_master_release;
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hub->master.n_links = links;
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hub->master.read = hub_master_read;
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hub->master.write = hub_master_write;
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hub->master.send_break = hub_master_break;
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hub->master.link_enable = hub_master_link_enable;
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dev_set_drvdata(dev, hub);
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hub_master_init(hub);
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rc = fsi_master_register(&hub->master);
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if (!rc)
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return 0;
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kfree(hub);
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err_release:
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fsi_slave_release_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET,
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FSI_HUB_LINK_SIZE * links);
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return rc;
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}
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static int hub_master_remove(struct device *dev)
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{
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struct fsi_master_hub *hub = dev_get_drvdata(dev);
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fsi_master_unregister(&hub->master);
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fsi_slave_release_range(hub->upstream->slave, hub->addr, hub->size);
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return 0;
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}
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static struct fsi_device_id hub_master_ids[] = {
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{
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.engine_type = FSI_ENGID_HUB_MASTER,
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.version = FSI_VERSION_ANY,
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},
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{ 0 }
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};
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static struct fsi_driver hub_master_driver = {
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.id_table = hub_master_ids,
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.drv = {
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.name = "fsi-master-hub",
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.bus = &fsi_bus_type,
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.probe = hub_master_probe,
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.remove = hub_master_remove,
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}
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};
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module_fsi_driver(hub_master_driver);
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MODULE_LICENSE("GPL");
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