linux_dsm_epyc7002/drivers/clk/hisilicon/Makefile

#
# Hisilicon Clock specific Makefile
#

obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o

obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2)	+= clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300)	+= crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200)	+= crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o
obj-$(CONFIG_RESET_HISI)	+= reset.o
obj-$(CONFIG_STUB_CLK_HI6220)	+= clk-hi6220-stub.o
clk: hisilicon: add common clock support Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> 2013-11-13 07:51:23 +07:00			`#`
			`# Hisilicon Clock specific Makefile`
			`#`

clk: hi6220: Clock driver support for Hisilicon hi6220 SoC Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> 2015-05-29 09:08:38 +07:00			`obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o`
clk: hip04: add clock driver Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> 2013-12-24 16:33:54 +07:00
			`obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o`
			`obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o`
clk: hisi: add clk-hix5hd2.c Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> 2014-04-21 11:07:27 +07:00			`obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o`
clk: hisilicon: add CRG driver for Hi3516CV300 SoC Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-11-14 09:49:54 +07:00			`obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o`
clk: hisilicon: add CRG driver for hi3519 soc The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-04-23 14:40:30 +07:00			`obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o`
clk: hisilicon: Add clock driver for hi3660 SoC Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-12-29 09:33:25 +07:00			`obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o`
clk: hisilicon: add CRG driver for Hi3798CV200 SoC Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-10-29 13:13:37 +07:00			`obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o`
clk: Hi6220: separately build stub clock driver The previous code, kernel builds Hi6220's common clock driver and stub clock driver together. Stub clock driver has introduced the dependency with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default. So separately build stub clock driver and common clock driver for Hi6220; and only let stub clock driver has the dependency with CONFIG_MAILBOX. Signed-off-by: Leo Yan <leo.yan@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-09-02 09:57:47 +07:00			`obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o`
reset: hisilicon: add reset controller driver for hisilicon SOCs In most of hisilicon SOCs, reset controller and clock provider are combined together as a block named CRG (Clock and Reset Generator). This patch mainly implements the reset function. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2016-04-23 14:40:28 +07:00			`obj-$(CONFIG_RESET_HISI) += reset.o`
clk: Hi6220: separately build stub clock driver The previous code, kernel builds Hi6220's common clock driver and stub clock driver together. Stub clock driver has introduced the dependency with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default. So separately build stub clock driver and common clock driver for Hi6220; and only let stub clock driver has the dependency with CONFIG_MAILBOX. Signed-off-by: Leo Yan <leo.yan@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> 2015-09-02 09:57:47 +07:00			`obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o`