2019-05-27 13:55:01 +07:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2018-02-14 07:07:45 +07:00
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/*
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* Marvell 88E6xxx Switch PTP support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 National Instruments
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* Erik Hons <erik.hons@ni.com>
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* Brandon Streiff <brandon.streiff@ni.com>
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* Dane Wagner <dane.wagner@ni.com>
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*/
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#ifndef _MV88E6XXX_PTP_H
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#define _MV88E6XXX_PTP_H
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#include "chip.h"
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/* Offset 0x00: TAI Global Config */
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#define MV88E6XXX_TAI_CFG 0x00
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2018-02-14 07:07:47 +07:00
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#define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000
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#define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000
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#define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000
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#define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000
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#define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400
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#define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200
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#define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100
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#define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080
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#define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008
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#define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004
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#define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002
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#define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001
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2018-02-14 07:07:45 +07:00
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/* Offset 0x01: Timestamp Clock Period (ps) */
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#define MV88E6XXX_TAI_CLOCK_PERIOD 0x01
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/* Offset 0x02/0x03: Trigger Generation Amount */
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#define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02
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#define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03
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/* Offset 0x04: Clock Compensation */
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#define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04
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/* Offset 0x05: Trigger Configuration */
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#define MV88E6XXX_TAI_TRIG_CFG 0x05
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/* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
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#define MV88E6XXX_TAI_IRL_AMOUNT 0x06
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/* Offset 0x07: Ingress Rate Limiter Compensation */
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#define MV88E6XXX_TAI_IRL_COMP 0x07
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/* Offset 0x08: Ingress Rate Limiter Compensation */
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#define MV88E6XXX_TAI_IRL_COMP_PS 0x08
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/* Offset 0x09: Event Status */
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#define MV88E6XXX_TAI_EVENT_STATUS 0x09
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#define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000
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#define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200
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#define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100
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#define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff
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2018-02-14 07:07:45 +07:00
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/* Offset 0x0A/0x0B: Event Time */
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#define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a
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#define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b
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/* Offset 0x0E/0x0F: PTP Global Time */
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#define MV88E6XXX_TAI_TIME_LO 0x0e
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#define MV88E6XXX_TAI_TIME_HI 0x0f
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/* Offset 0x10/0x11: Trig Generation Time */
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#define MV88E6XXX_TAI_TRIG_TIME_LO 0x10
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#define MV88E6XXX_TAI_TRIG_TIME_HI 0x11
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/* Offset 0x12: Lock Status */
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#define MV88E6XXX_TAI_LOCK_STATUS 0x12
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2018-07-19 03:38:22 +07:00
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/* Offset 0x00: Ether Type */
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#define MV88E6XXX_PTP_GC_ETYPE 0x00
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2018-07-19 03:38:25 +07:00
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/* 6165 Global Control Registers */
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2018-07-19 03:38:26 +07:00
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/* Offset 0x00: Ether Type */
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#define MV88E6XXX_PTP_GC_ETYPE 0x00
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2018-07-19 03:38:22 +07:00
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/* Offset 0x01: Message ID */
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#define MV88E6XXX_PTP_GC_MESSAGE_ID 0x01
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/* Offset 0x02: Time Stamp Arrive Time */
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#define MV88E6XXX_PTP_GC_TS_ARR_PTR 0x02
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/* Offset 0x03: Port Arrival Interrupt Enable */
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#define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN 0x03
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/* Offset 0x04: Port Departure Interrupt Enable */
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#define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN 0x04
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/* Offset 0x05: Configuration */
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#define MV88E6XXX_PTP_GC_CONFIG 0x05
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#define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1)
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#define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0)
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/* Offset 0x8: Interrupt Status */
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#define MV88E6XXX_PTP_GC_INT_STATUS 0x08
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/* Offset 0x9/0xa: Global Time */
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#define MV88E6XXX_PTP_GC_TIME_LO 0x09
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#define MV88E6XXX_PTP_GC_TIME_HI 0x0A
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2018-07-19 03:38:25 +07:00
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/* 6165 Per Port Registers */
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/* Offset 0: Arrival Time 0 Status */
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#define MV88E6165_PORT_PTP_ARR0_STS 0x00
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/* Offset 0x01/0x02: PTP Arrival 0 Time */
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#define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01
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#define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02
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/* Offset 0x03: PTP Arrival 0 Sequence ID */
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#define MV88E6165_PORT_PTP_ARR0_SEQID 0x03
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/* Offset 0x04: PTP Arrival 1 Status */
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#define MV88E6165_PORT_PTP_ARR1_STS 0x04
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/* Offset 0x05/0x6E: PTP Arrival 1 Time */
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#define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05
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#define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06
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/* Offset 0x07: PTP Arrival 1 Sequence ID */
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#define MV88E6165_PORT_PTP_ARR1_SEQID 0x07
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/* Offset 0x08: PTP Departure Status */
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#define MV88E6165_PORT_PTP_DEP_STS 0x08
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/* Offset 0x09/0x0a: PTP Deperture Time */
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#define MV88E6165_PORT_PTP_DEP_TIME_LO 0x09
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#define MV88E6165_PORT_PTP_DEP_TIME_HI 0x0a
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/* Offset 0x0b: PTP Departure Sequence ID */
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#define MV88E6165_PORT_PTP_DEP_SEQID 0x0b
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/* Offset 0x0d: Port Status */
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#define MV88E6164_PORT_STATUS 0x0d
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2018-02-14 07:07:45 +07:00
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#ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
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2018-02-14 07:07:50 +07:00
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long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);
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2018-02-14 07:07:45 +07:00
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int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);
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void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
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2018-02-14 07:07:50 +07:00
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#define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \
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ptp_clock_info)
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2018-07-19 03:38:20 +07:00
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extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops;
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2018-07-19 03:38:22 +07:00
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extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops;
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2018-07-19 03:38:20 +07:00
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2018-02-14 07:07:45 +07:00
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#else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
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2018-02-22 18:44:40 +07:00
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static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)
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2018-02-14 07:07:50 +07:00
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{
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return -1;
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}
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2018-02-14 07:07:45 +07:00
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static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
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{
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return 0;
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}
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2018-02-22 18:44:40 +07:00
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static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
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2018-02-14 07:07:45 +07:00
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{
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}
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2018-07-19 03:38:20 +07:00
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static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {};
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2018-07-19 03:38:22 +07:00
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static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {};
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2018-07-19 03:38:20 +07:00
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2018-02-14 07:07:45 +07:00
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#endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
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#endif /* _MV88E6XXX_PTP_H */
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