linux_dsm_epyc7002/arch/arm/boot/dts/tegra20-colibri.dtsi

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
// SPDX-License-Identifier: GPL-2.0
#include "tegra20.dtsi"
/*
* Toradex Colibri T20 Module Device Tree
* Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
* Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
* Colibri T20 512MB IT V1.2A
*/
/ {
memory@0 {
/*
* Set memory to 256 MB to be safe as this could be used on
* 256 or 512 MB module. It is expected from bootloader
* to fix this up for 512 MB version.
*/
reg = <0x00000000 0x10000000>;
};
host1x@50000000 {
hdmi@54280000 {
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
pll-supply = <&reg_1v8_avdd_hdmi_pll>;
vdd-supply = <&reg_3v3_avdd_hdmi>;
};
};
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
/* Analogue Audio AC97 to WM9712 (On-module) */
audio-refclk {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
* (All on-module), SODIMM Pin 45 Wakeup
*/
gpio-uac {
nvidia,pins = "uac";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* Buffer Enables for nPWE and RDnWR (On-module,
* see GPIO hogging further down below)
*/
gpio-pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
* SYS_CLK_REQ (All on-module)
*/
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* Colibri Address/Data Bus (GMI)
* Note: spid and spie optionally used for SPI1
*/
gmi {
nvidia,pins = "atc", "atd", "ate", "dap1",
"dap2", "dap4", "gmd", "gpu",
"irrx", "irtx", "spia", "spib",
"spic", "spid", "spie", "uca",
"ucb";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Further pins may be used as GPIOs */
gmi-gpio1 {
nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
nvidia,function = "hdmi";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
gmi-gpio2 {
nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
nvidia,function = "rsvd4";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri BL_ON */
bl-on {
nvidia,pins = "dta";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri Backlight PWM<A>, PWM<B> */
pwm-a-b {
nvidia,pins = "sdc";
nvidia,function = "pwm";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri DDC */
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* Colibri EXT_IO*
* Note: dtf optionally used for I2C3
*/
ext-io {
nvidia,pins = "dtf", "spdi";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* Colibri Ethernet (On-module)
* ULPI EHCI instance 1 USB2_DP/N -> AX88772B
*/
ulpi {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
ulpi-refclk {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Colibri HOTPLUG_DETECT (HDMI) */
hotplug-detect {
nvidia,pins = "hdint";
nvidia,function = "hdmi";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri I2C */
i2c {
nvidia,pins = "rm";
nvidia,function = "i2c1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
* today's display need DE, disable LCD_M1
*/
lm1 {
nvidia,pins = "lm1";
nvidia,function = "rsvd3";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri LCD (L_* resp. LDD<*>) */
lcd {
nvidia,pins = "ld0", "ld1", "ld2", "ld3",
"ld4", "ld5", "ld6", "ld7",
"ld8", "ld9", "ld10", "ld11",
"ld12", "ld13", "ld14", "ld15",
"ld16", "ld17", "lhs", "lsc0",
"lspi", "lvs";
nvidia,function = "displaya";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri LCD (Optional 24 BPP Support) */
lcd-24 {
nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
"lpp", "lvp1";
nvidia,function = "displaya";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri MMC */
mmc {
nvidia,pins = "atb", "gma";
nvidia,function = "sdio4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri MMCCD */
mmccd {
nvidia,pins = "gmb";
nvidia,function = "gmi_int";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri MMC (Optional 8-bit) */
mmc-8bit {
nvidia,pins = "gme";
nvidia,function = "sdio4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* Colibri Parallel Camera (Optional)
* pins multiplexed with others and therefore disabled
* Note: dta used for BL_ON by default
*/
cif-mclk {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
cif {
nvidia,pins = "dtb", "dtc", "dtd";
nvidia,function = "vi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri PWM<C>, PWM<D> */
pwm-c-d {
nvidia,pins = "sdb", "sdd";
nvidia,function = "pwm";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri SSP */
ssp {
nvidia,pins = "slxa", "slxc", "slxd", "slxk";
nvidia,function = "spi4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri UART-A */
uart-a {
nvidia,pins = "sdio1";
nvidia,function = "uarta";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
uart-a-dsr {
nvidia,pins = "lpw1";
nvidia,function = "rsvd3";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
uart-a-dcd {
nvidia,pins = "lpw2";
nvidia,function = "hdmi";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri UART-B */
uart-b {
nvidia,pins = "gmc";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri UART-C */
uart-c {
nvidia,pins = "uad";
nvidia,function = "irda";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri USB_CDET */
usb-cdet {
nvidia,pins = "spdo";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri USBH_OC */
usbh-oc {
nvidia,pins = "spih";
nvidia,function = "spi2_alt";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri USBH_PEN */
usbh-pen {
nvidia,pins = "spig";
nvidia,function = "spi2_alt";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Colibri VGA not supported */
vga {
nvidia,pins = "crtp";
nvidia,function = "crt";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* I2C3 (Optional) */
i2c3 {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* JTAG_RTCK */
jtag-rtck {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
* (All On-module)
*/
gpio-gpv {
nvidia,pins = "gpv";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
* (All On-module); Colibri CAN_INT
*/
gpio-dte {
nvidia,pins = "dte";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* NAND (On-module) */
nand {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "nand";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* Onewire (Optional) */
owr {
nvidia,pins = "owc";
nvidia,function = "owr";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/* Power I2C (On-module) */
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/* RESET_OUT */
reset-out {
nvidia,pins = "ata";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* SPI1 (Optional)
* Note: spid and spie used for Colibri Address/Data
* Bus (GMI)
*/
spi1 {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
/*
* THERMD_ALERT# (On-module), unlatched I2C address pin
* of LM95245 temperature sensor therefore requires
* disabling for now
*/
lvp0 {
nvidia,pins = "lvp0";
nvidia,function = "rsvd3";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};
tegra_ac97: ac97@70002000 {
status = "okay";
nvidia,codec-reset-gpio =
<&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
nvidia,codec-sync-gpio =
<&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
};
serial@70006040 {
compatible = "nvidia,tegra20-hsuart";
};
serial@70006300 {
compatible = "nvidia,tegra20-hsuart";
};
nand-controller@70008000 {
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-bus-width = <8>;
nand-on-flash-bbt;
nand-ecc-algo = "bch";
nand-is-boot-medium;
nand-ecc-maximize;
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
};
};
/*
* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
* board)
*/
i2c@7000c000 {
clock-frequency = <400000>;
};
/* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
hdmi_ddc: i2c@7000c400 {
clock-frequency = <10000>;
};
/* GEN2_I2C: unused */
/* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
/* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
pmic@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
sys-supply = <&reg_module_3v3>;
vin-sm0-supply = <&reg_3v3_vsys>;
vin-sm1-supply = <&reg_3v3_vsys>;
vin-sm2-supply = <&reg_3v3_vsys>;
vinldo01-supply = <&reg_1v8_vdd_ddr2>;
vinldo23-supply = <&reg_module_3v3>;
vinldo4-supply = <&reg_module_3v3>;
vinldo678-supply = <&reg_module_3v3>;
vinldo9-supply = <&reg_module_3v3>;
regulators {
reg_3v3_vsys: sys {
regulator-name = "VSYS_3.3V";
regulator-always-on;
};
sm0 {
regulator-name = "VDD_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
sm1 {
regulator-name = "VDD_CPU_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
reg_1v8_vdd_ddr2: sm2 {
regulator-name = "VDD_DDR2_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
/* LDO0 is not connected to anything */
/*
* +3.3V_ENABLE_N switching via FET:
* AVDD_AUDIO_S and +3.3V
* see also +3.3V fixed supply
*/
ldo1 {
regulator-name = "AVDD_PLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo2 {
regulator-name = "VDD_RTC_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
/* LDO3 is not connected to anything */
ldo4 {
regulator-name = "VDDIO_SYS_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
/* Switched via FET from regular +3.3V */
ldo5 {
regulator-name = "+3.3V_USB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo6 {
regulator-name = "AVDD_VDAC_2.85V";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
reg_3v3_avdd_hdmi: ldo7 {
regulator-name = "AVDD_HDMI_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_1v8_avdd_hdmi_pll: ldo8 {
regulator-name = "AVDD_HDMI_PLL_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo9 {
regulator-name = "VDDIO_RX_DDR_2.85V";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
ldo_rtc {
regulator-name = "VCC_BATT";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* LM95245 temperature sensor */
temp-sensor@4c {
compatible = "national,lm95245";
reg = <0x4c>;
};
};
pmc@7000e400 {
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
i2c-thermtrip {
nvidia,i2c-controller-id = <3>;
nvidia,bus-addr = <0x34>;
nvidia,reg-addr = <0x14>;
nvidia,reg-data = <0x8>;
};
};
memory-controller@7000f400 {
emc-table@83250 {
reg = <83250>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = <83250>;
nvidia,emc-registers = <0x00000005 0x00000011
0x00000004 0x00000002 0x00000004 0x00000004
0x00000001 0x0000000a 0x00000002 0x00000002
0x00000001 0x00000001 0x00000003 0x00000004
0x00000003 0x00000009 0x0000000c 0x0000025f
0x00000000 0x00000003 0x00000003 0x00000002
0x00000002 0x00000001 0x00000008 0x000000c8
0x00000003 0x00000005 0x00000003 0x0000000c
0x00000002 0x00000000 0x00000000 0x00000002
0x00000000 0x00000000 0x00000083 0x00520006
0x00000010 0x00000008 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
emc-table@133200 {
reg = <133200>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = <133200>;
nvidia,emc-registers = <0x00000008 0x00000019
0x00000006 0x00000002 0x00000004 0x00000004
0x00000001 0x0000000a 0x00000002 0x00000002
0x00000002 0x00000001 0x00000003 0x00000004
0x00000003 0x00000009 0x0000000c 0x0000039f
0x00000000 0x00000003 0x00000003 0x00000002
0x00000002 0x00000001 0x00000008 0x000000c8
0x00000003 0x00000007 0x00000003 0x0000000c
0x00000002 0x00000000 0x00000000 0x00000002
0x00000000 0x00000000 0x00000083 0x00510006
0x00000010 0x00000008 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
emc-table@166500 {
reg = <166500>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = <166500>;
nvidia,emc-registers = <0x0000000a 0x00000021
0x00000008 0x00000003 0x00000004 0x00000004
0x00000002 0x0000000a 0x00000003 0x00000003
0x00000002 0x00000001 0x00000003 0x00000004
0x00000003 0x00000009 0x0000000c 0x000004df
0x00000000 0x00000003 0x00000003 0x00000003
0x00000003 0x00000001 0x00000009 0x000000c8
0x00000003 0x00000009 0x00000004 0x0000000c
0x00000002 0x00000000 0x00000000 0x00000002
0x00000000 0x00000000 0x00000083 0x004f0006
0x00000010 0x00000008 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
emc-table@333000 {
reg = <333000>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = <333000>;
nvidia,emc-registers = <0x00000014 0x00000041
0x0000000f 0x00000005 0x00000004 0x00000005
0x00000003 0x0000000a 0x00000005 0x00000005
0x00000004 0x00000001 0x00000003 0x00000004
0x00000003 0x00000009 0x0000000c 0x000009ff
0x00000000 0x00000003 0x00000003 0x00000005
0x00000005 0x00000001 0x0000000e 0x000000c8
0x00000003 0x00000011 0x00000006 0x0000000c
0x00000002 0x00000000 0x00000000 0x00000002
0x00000000 0x00000000 0x00000083 0x00380006
0x00000010 0x00000008 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
};
/* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
usb@c5004000 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
asix@1 {
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
};
usb-phy@c5004000 {
status = "okay";
nvidia,phy-reset-gpio =
<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
vbus-supply = <&reg_lan_v_bus>;
};
clk32k_in: xtal3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
reg_lan_v_bus: regulator-lan-v-bus {
compatible = "regulator-fixed";
regulator-name = "LAN_V_BUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
nvidia,model = "Toradex Colibri T20";
nvidia,audio-routing =
"Headphone", "HPOUTL",
"Headphone", "HPOUTR",
"LineIn", "LINEINL",
"LineIn", "LINEINR",
"Mic", "MIC1";
nvidia,ac97-controller = <&tegra_ac97>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};
&gpio {
lan-reset-n {
gpio-hog;
gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "LAN_RESET#";
};
/* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
npwe {
gpio-hog;
gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "Tri-state nPWE";
};
/* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
rdnwr {
gpio-hog;
gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "Not tri-state RDnWR";
};
};