drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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/*
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2018-06-28 02:26:09 +07:00
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-06-28 02:26:09 +07:00
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#include <linux/kthread.h>
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#include <uapi/linux/sched/types.h>
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2016-10-19 17:28:27 +07:00
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#include <drm/drm_of.h>
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|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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#include "msm_drv.h"
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2016-03-16 23:56:12 +07:00
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#include "msm_debugfs.h"
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2016-03-16 02:35:08 +07:00
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#include "msm_fence.h"
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2018-11-29 22:27:22 +07:00
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#include "msm_gem.h"
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2013-07-19 23:59:32 +07:00
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#include "msm_gpu.h"
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2013-12-01 04:12:10 +07:00
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#include "msm_kms.h"
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2018-11-15 05:08:04 +07:00
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#include "adreno/adreno_gpu.h"
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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2016-06-02 01:02:02 +07:00
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/*
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* MSM driver version:
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* - 1.0.0 - initial interface
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* - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
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2016-09-17 05:37:44 +07:00
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* - 1.2.0 - adds explicit fence support for submit ioctl
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2017-10-21 00:06:55 +07:00
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* - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
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* SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
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* MSM_GEM_INFO ioctl.
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2018-11-29 22:30:04 +07:00
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* - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
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* GEM object's debug name
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2016-06-02 01:02:02 +07:00
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*/
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#define MSM_VERSION_MAJOR 1
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2018-11-29 22:30:04 +07:00
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#define MSM_VERSION_MINOR 4
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2016-06-02 01:02:02 +07:00
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#define MSM_VERSION_PATCHLEVEL 0
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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static const struct drm_mode_config_funcs mode_config_funcs = {
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.fb_create = msm_framebuffer_create,
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2017-12-06 01:24:59 +07:00
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.output_poll_changed = drm_fb_helper_output_poll_changed,
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2017-10-25 23:30:51 +07:00
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.atomic_check = drm_atomic_helper_check,
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2018-03-01 02:19:05 +07:00
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.atomic_commit = drm_atomic_helper_commit,
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};
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static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
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.atomic_commit_tail = msm_atomic_commit_tail,
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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};
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#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
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static bool reglog = false;
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MODULE_PARM_DESC(reglog, "Enable register read/write logging");
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module_param(reglog, bool, 0600);
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#else
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#define reglog 0
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#endif
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2015-07-13 13:42:07 +07:00
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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2015-01-31 05:05:41 +07:00
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static bool fbdev = true;
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MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
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module_param(fbdev, bool, 0600);
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#endif
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2014-09-09 01:24:57 +07:00
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static char *vram = "16m";
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2016-02-04 02:02:04 +07:00
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MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
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2013-11-17 00:56:06 +07:00
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module_param(vram, charp, 0);
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2016-11-05 22:08:12 +07:00
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bool dumpstate = false;
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MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
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module_param(dumpstate, bool, 0600);
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2017-07-07 03:33:44 +07:00
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static bool modeset = true;
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MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
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module_param(modeset, bool, 0600);
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2014-03-04 02:19:12 +07:00
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/*
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* Util/helpers:
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*/
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2018-08-07 00:33:21 +07:00
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int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
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{
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struct property *prop;
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const char *name;
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struct clk_bulk_data *local;
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int i = 0, ret, count;
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count = of_property_count_strings(dev->of_node, "clock-names");
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if (count < 1)
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return 0;
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local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
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count, GFP_KERNEL);
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if (!local)
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return -ENOMEM;
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of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
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local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
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if (!local[i].id) {
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devm_kfree(dev, local);
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return -ENOMEM;
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}
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i++;
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}
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ret = devm_clk_bulk_get(dev, count, local);
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if (ret) {
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for (i = 0; i < count; i++)
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devm_kfree(dev, (void *) local[i].id);
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devm_kfree(dev, local);
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return ret;
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}
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*bulk = local;
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return count;
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}
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struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
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const char *name)
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{
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int i;
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char n[32];
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snprintf(n, sizeof(n), "%s_clk", name);
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for (i = 0; bulk && i < count; i++) {
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if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
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return bulk[i].clk;
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}
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return NULL;
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}
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2017-01-30 23:30:58 +07:00
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struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
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{
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struct clk *clk;
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char name2[32];
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clk = devm_clk_get(&pdev->dev, name);
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if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
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return clk;
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snprintf(name2, sizeof(name2), "%s_clk", name);
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clk = devm_clk_get(&pdev->dev, name2);
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if (!IS_ERR(clk))
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dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
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"\"%s\" instead of \"%s\"\n", name, name2);
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return clk;
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}
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|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
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void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
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const char *dbgname)
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{
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struct resource *res;
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unsigned long size;
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void __iomem *ptr;
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if (name)
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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else
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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2018-10-21 00:49:26 +07:00
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DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
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return ERR_PTR(-EINVAL);
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}
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size = resource_size(res);
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ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
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if (!ptr) {
|
2018-10-21 00:49:26 +07:00
|
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|
DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reglog)
|
2015-04-09 21:39:51 +07:00
|
|
|
printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
|
|
|
return ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void msm_writel(u32 data, void __iomem *addr)
|
|
|
|
{
|
|
|
|
if (reglog)
|
2015-04-09 21:39:51 +07:00
|
|
|
printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
writel(data, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 msm_readl(const void __iomem *addr)
|
|
|
|
{
|
|
|
|
u32 val = readl(addr);
|
|
|
|
if (reglog)
|
2017-02-28 19:55:54 +07:00
|
|
|
pr_err("IO:R %p %08x\n", addr, val);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
struct msm_vblank_work {
|
|
|
|
struct work_struct work;
|
2015-07-28 00:49:45 +07:00
|
|
|
int crtc_id;
|
|
|
|
bool enable;
|
2018-12-15 06:57:55 +07:00
|
|
|
struct msm_drm_private *priv;
|
2015-07-28 00:49:45 +07:00
|
|
|
};
|
|
|
|
|
2018-12-15 06:57:52 +07:00
|
|
|
static void vblank_ctrl_worker(struct work_struct *work)
|
2015-07-28 00:49:45 +07:00
|
|
|
{
|
2018-12-15 06:57:55 +07:00
|
|
|
struct msm_vblank_work *vbl_work = container_of(work,
|
|
|
|
struct msm_vblank_work, work);
|
|
|
|
struct msm_drm_private *priv = vbl_work->priv;
|
2015-07-28 00:49:45 +07:00
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
if (vbl_work->enable)
|
|
|
|
kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
|
|
|
|
else
|
|
|
|
kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
|
2015-07-28 00:49:45 +07:00
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
kfree(vbl_work);
|
2015-07-28 00:49:45 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
|
|
|
|
int crtc_id, bool enable)
|
|
|
|
{
|
2018-12-15 06:57:55 +07:00
|
|
|
struct msm_vblank_work *vbl_work;
|
2015-07-28 00:49:45 +07:00
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
|
|
|
|
if (!vbl_work)
|
2015-07-28 00:49:45 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
|
2015-07-28 00:49:45 +07:00
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
vbl_work->crtc_id = crtc_id;
|
|
|
|
vbl_work->enable = enable;
|
|
|
|
vbl_work->priv = priv;
|
2015-07-28 00:49:45 +07:00
|
|
|
|
2018-12-15 06:57:55 +07:00
|
|
|
queue_work(priv->wq, &vbl_work->work);
|
2015-07-28 00:49:45 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
static int msm_drm_uninit(struct device *dev)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
2016-05-02 12:35:54 +07:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct drm_device *ddev = platform_get_drvdata(pdev);
|
|
|
|
struct msm_drm_private *priv = ddev->dev_private;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
struct msm_kms *kms = priv->kms;
|
2018-06-22 03:06:10 +07:00
|
|
|
struct msm_mdss *mdss = priv->mdss;
|
2018-06-28 02:26:09 +07:00
|
|
|
int i;
|
2015-07-28 00:49:45 +07:00
|
|
|
|
|
|
|
/* We must cancel and cleanup any pending vblank enable/disable
|
|
|
|
* work before drm_irq_uninstall() to avoid work re-enabling an
|
|
|
|
* irq after uninstall has disabled it.
|
|
|
|
*/
|
2018-12-15 06:57:55 +07:00
|
|
|
|
|
|
|
flush_workqueue(priv->wq);
|
|
|
|
destroy_workqueue(priv->wq);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-12-15 06:57:54 +07:00
|
|
|
/* clean up event worker threads */
|
2018-06-28 02:26:09 +07:00
|
|
|
for (i = 0; i < priv->num_crtcs; i++) {
|
|
|
|
if (priv->event_thread[i].thread) {
|
2018-12-15 06:57:51 +07:00
|
|
|
kthread_destroy_worker(&priv->event_thread[i].worker);
|
2018-06-28 02:26:09 +07:00
|
|
|
priv->event_thread[i].thread = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-18 03:19:32 +07:00
|
|
|
msm_gem_shrinker_cleanup(ddev);
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
drm_kms_helper_poll_fini(ddev);
|
|
|
|
|
|
|
|
drm_dev_unregister(ddev);
|
2016-05-02 12:35:53 +07:00
|
|
|
|
2017-03-08 03:49:22 +07:00
|
|
|
msm_perf_debugfs_cleanup(priv);
|
|
|
|
msm_rd_debugfs_cleanup(priv);
|
|
|
|
|
2016-02-25 12:49:45 +07:00
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
|
|
|
if (fbdev && priv->fbdev)
|
2016-05-02 12:35:54 +07:00
|
|
|
msm_fbdev_free(ddev);
|
2016-02-25 12:49:45 +07:00
|
|
|
#endif
|
2018-10-05 03:24:36 +07:00
|
|
|
drm_atomic_helper_shutdown(ddev);
|
2016-05-02 12:35:54 +07:00
|
|
|
drm_mode_config_cleanup(ddev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
drm_irq_uninstall(ddev);
|
|
|
|
pm_runtime_put_sync(dev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2016-11-03 19:06:18 +07:00
|
|
|
if (kms && kms->funcs)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
kms->funcs->destroy(kms);
|
|
|
|
|
2013-11-17 00:56:06 +07:00
|
|
|
if (priv->vram.paddr) {
|
2016-08-04 03:46:00 +07:00
|
|
|
unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
|
2013-11-17 00:56:06 +07:00
|
|
|
drm_mm_takedown(&priv->vram.mm);
|
2016-05-02 12:35:54 +07:00
|
|
|
dma_free_attrs(dev, priv->vram.size, NULL,
|
2016-08-04 03:46:00 +07:00
|
|
|
priv->vram.paddr, attrs);
|
2013-11-17 00:56:06 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
component_unbind_all(dev, ddev);
|
2014-03-04 02:19:12 +07:00
|
|
|
|
2018-06-22 03:06:10 +07:00
|
|
|
if (mdss && mdss->funcs)
|
|
|
|
mdss->funcs->destroy(ddev);
|
2016-05-08 23:06:28 +07:00
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ddev->dev_private = NULL;
|
2018-09-26 18:48:59 +07:00
|
|
|
drm_dev_put(ddev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
|
|
|
kfree(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-06-28 01:26:24 +07:00
|
|
|
#define KMS_MDP4 4
|
|
|
|
#define KMS_MDP5 5
|
2018-06-28 02:26:09 +07:00
|
|
|
#define KMS_DPU 3
|
2018-06-28 01:26:24 +07:00
|
|
|
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
static int get_mdp_ver(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
2015-11-18 13:45:14 +07:00
|
|
|
|
|
|
|
return (int) (unsigned long) of_device_get_match_data(dev);
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
}
|
|
|
|
|
2015-03-04 03:04:25 +07:00
|
|
|
#include <linux/of_address.h>
|
|
|
|
|
2018-11-15 05:08:04 +07:00
|
|
|
bool msm_use_mmu(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
|
|
|
|
/* a2xx comes with its own MMU */
|
|
|
|
return priv->is_a2xx || iommu_present(&platform_bus_type);
|
|
|
|
}
|
|
|
|
|
2015-03-04 03:04:24 +07:00
|
|
|
static int msm_init_vram(struct drm_device *dev)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
2015-03-04 03:04:24 +07:00
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2015-11-18 13:45:14 +07:00
|
|
|
struct device_node *node;
|
2015-03-04 03:04:25 +07:00
|
|
|
unsigned long size = 0;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* In the device-tree world, we could have a 'memory-region'
|
|
|
|
* phandle, which gives us a link to our "vram". Allocating
|
|
|
|
* is all nicely abstracted behind the dma api, but we need
|
|
|
|
* to know the entire size to allocate it all in one go. There
|
|
|
|
* are two cases:
|
|
|
|
* 1) device with no IOMMU, in which case we need exclusive
|
|
|
|
* access to a VRAM carveout big enough for all gpu
|
|
|
|
* buffers
|
|
|
|
* 2) device with IOMMU, but where the bootloader puts up
|
|
|
|
* a splash screen. In this case, the VRAM carveout
|
|
|
|
* need only be large enough for fbdev fb. But we need
|
|
|
|
* exclusive access to the buffer to avoid the kernel
|
|
|
|
* using those pages for other purposes (which appears
|
|
|
|
* as corruption on screen before we have a chance to
|
|
|
|
* load and do initial modeset)
|
|
|
|
*/
|
|
|
|
|
|
|
|
node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
|
|
|
|
if (node) {
|
|
|
|
struct resource r;
|
|
|
|
ret = of_address_to_resource(node, 0, &r);
|
2016-07-04 15:49:50 +07:00
|
|
|
of_node_put(node);
|
2015-03-04 03:04:25 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
size = r.end - r.start;
|
2015-04-09 21:39:51 +07:00
|
|
|
DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2015-11-18 13:45:14 +07:00
|
|
|
/* if we have no IOMMU, then we need to use carveout allocator.
|
|
|
|
* Grab the entire CMA chunk carved out in early startup in
|
|
|
|
* mach-msm:
|
|
|
|
*/
|
2018-11-15 05:08:04 +07:00
|
|
|
} else if (!msm_use_mmu(dev)) {
|
2015-03-04 03:04:25 +07:00
|
|
|
DRM_INFO("using %s VRAM carveout\n", vram);
|
|
|
|
size = memparse(vram, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size) {
|
2016-08-04 03:46:00 +07:00
|
|
|
unsigned long attrs = 0;
|
2013-11-17 00:56:06 +07:00
|
|
|
void *p;
|
|
|
|
|
|
|
|
priv->vram.size = size;
|
|
|
|
|
|
|
|
drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
|
2017-06-14 05:52:54 +07:00
|
|
|
spin_lock_init(&priv->vram.lock);
|
2013-11-17 00:56:06 +07:00
|
|
|
|
2016-08-04 03:46:00 +07:00
|
|
|
attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
|
|
|
|
attrs |= DMA_ATTR_WRITE_COMBINE;
|
2013-11-17 00:56:06 +07:00
|
|
|
|
|
|
|
/* note that for no-kernel-mapping, the vaddr returned
|
|
|
|
* is bogus, but non-null if allocation succeeded:
|
|
|
|
*/
|
|
|
|
p = dma_alloc_attrs(dev->dev, size,
|
2016-08-04 03:46:00 +07:00
|
|
|
&priv->vram.paddr, GFP_KERNEL, attrs);
|
2013-11-17 00:56:06 +07:00
|
|
|
if (!p) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
|
2013-11-17 00:56:06 +07:00
|
|
|
priv->vram.paddr = 0;
|
2015-03-04 03:04:24 +07:00
|
|
|
return -ENOMEM;
|
2013-11-17 00:56:06 +07:00
|
|
|
}
|
|
|
|
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
|
2013-11-17 00:56:06 +07:00
|
|
|
(uint32_t)priv->vram.paddr,
|
|
|
|
(uint32_t)(priv->vram.paddr + size));
|
|
|
|
}
|
|
|
|
|
2015-03-04 03:04:25 +07:00
|
|
|
return ret;
|
2015-03-04 03:04:24 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
static int msm_drm_init(struct device *dev, struct drm_driver *drv)
|
2015-03-04 03:04:24 +07:00
|
|
|
{
|
2016-05-02 12:35:54 +07:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct drm_device *ddev;
|
2015-03-04 03:04:24 +07:00
|
|
|
struct msm_drm_private *priv;
|
|
|
|
struct msm_kms *kms;
|
2018-06-22 03:06:10 +07:00
|
|
|
struct msm_mdss *mdss;
|
2018-06-28 02:26:09 +07:00
|
|
|
int ret, i;
|
|
|
|
struct sched_param param;
|
2015-03-04 03:04:24 +07:00
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ddev = drm_dev_alloc(drv, dev);
|
2016-09-21 21:59:19 +07:00
|
|
|
if (IS_ERR(ddev)) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
|
2016-09-21 21:59:19 +07:00
|
|
|
return PTR_ERR(ddev);
|
2016-05-02 12:35:54 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, ddev);
|
|
|
|
|
2015-03-04 03:04:24 +07:00
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv) {
|
2018-06-28 01:35:28 +07:00
|
|
|
ret = -ENOMEM;
|
2018-09-26 18:48:59 +07:00
|
|
|
goto err_put_drm_dev;
|
2015-03-04 03:04:24 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ddev->dev_private = priv;
|
2016-05-18 03:19:32 +07:00
|
|
|
priv->dev = ddev;
|
2015-03-04 03:04:24 +07:00
|
|
|
|
2018-06-28 02:26:09 +07:00
|
|
|
switch (get_mdp_ver(pdev)) {
|
|
|
|
case KMS_MDP5:
|
|
|
|
ret = mdp5_mdss_init(ddev);
|
|
|
|
break;
|
|
|
|
case KMS_DPU:
|
|
|
|
ret = dpu_mdss_init(ddev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
2018-06-28 01:35:28 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_free_priv;
|
2016-05-08 23:06:28 +07:00
|
|
|
|
2018-06-22 03:06:10 +07:00
|
|
|
mdss = priv->mdss;
|
|
|
|
|
2015-03-04 03:04:24 +07:00
|
|
|
priv->wq = alloc_ordered_workqueue("msm", 0);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&priv->inactive_list);
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
drm_mode_config_init(ddev);
|
2014-03-04 02:19:12 +07:00
|
|
|
|
|
|
|
/* Bind all our sub-components: */
|
2016-05-02 12:35:54 +07:00
|
|
|
ret = component_bind_all(dev, ddev);
|
2018-06-28 01:35:28 +07:00
|
|
|
if (ret)
|
|
|
|
goto err_destroy_mdss;
|
2014-03-04 02:19:12 +07:00
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ret = msm_init_vram(ddev);
|
2015-05-08 02:20:13 +07:00
|
|
|
if (ret)
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
2015-05-08 02:20:13 +07:00
|
|
|
|
2016-05-18 03:19:32 +07:00
|
|
|
msm_gem_shrinker_init(ddev);
|
|
|
|
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
switch (get_mdp_ver(pdev)) {
|
2018-06-28 01:26:24 +07:00
|
|
|
case KMS_MDP4:
|
2016-05-02 12:35:54 +07:00
|
|
|
kms = mdp4_kms_init(ddev);
|
2016-05-08 23:06:28 +07:00
|
|
|
priv->kms = kms;
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
break;
|
2018-06-28 01:26:24 +07:00
|
|
|
case KMS_MDP5:
|
2016-06-14 19:54:54 +07:00
|
|
|
kms = mdp5_kms_init(ddev);
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
break;
|
2018-06-28 02:26:09 +07:00
|
|
|
case KMS_DPU:
|
|
|
|
kms = dpu_kms_init(ddev);
|
|
|
|
priv->kms = kms;
|
|
|
|
break;
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
default:
|
2018-12-04 22:16:58 +07:00
|
|
|
/* valid only for the dummy headless case, where of_node=NULL */
|
|
|
|
WARN_ON(dev->of_node);
|
|
|
|
kms = NULL;
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
if (IS_ERR(kms)) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to load kms\n");
|
2013-09-17 04:19:54 +07:00
|
|
|
ret = PTR_ERR(kms);
|
2018-11-22 08:52:35 +07:00
|
|
|
priv->kms = NULL;
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2018-06-12 04:13:20 +07:00
|
|
|
/* Enable normalization of plane zpos */
|
|
|
|
ddev->mode_config.normalize_zpos = true;
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
if (kms) {
|
|
|
|
ret = kms->funcs->hw_init(kms);
|
|
|
|
if (ret) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ddev->mode_config.funcs = &mode_config_funcs;
|
2018-03-01 02:19:05 +07:00
|
|
|
ddev->mode_config.helper_private = &mode_config_helper_funcs;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-06-28 02:26:09 +07:00
|
|
|
/**
|
|
|
|
* this priority was found during empiric testing to have appropriate
|
|
|
|
* realtime scheduling to process display updates and interact with
|
|
|
|
* other real time and normal priority task
|
|
|
|
*/
|
|
|
|
param.sched_priority = 16;
|
|
|
|
for (i = 0; i < priv->num_crtcs; i++) {
|
|
|
|
/* initialize event thread */
|
|
|
|
priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
|
|
|
|
kthread_init_worker(&priv->event_thread[i].worker);
|
|
|
|
priv->event_thread[i].dev = ddev;
|
|
|
|
priv->event_thread[i].thread =
|
|
|
|
kthread_run(kthread_worker_fn,
|
|
|
|
&priv->event_thread[i].worker,
|
|
|
|
"crtc_event:%d", priv->event_thread[i].crtc_id);
|
2018-10-11 04:11:16 +07:00
|
|
|
if (IS_ERR(priv->event_thread[i].thread)) {
|
drm pull request for 4.21-rc1
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iQIcBAABAgAGBQJcExwOAAoJEAx081l5xIa+euIP/1NZZvSB+bsCtOwDG8I6uWsS
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4abF6NadivYJ4cXhJ1ddIHOFMVDcAsyMWNDb93NwPwncCsQ0jt5FFOsrCyj6BGY+
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Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Core:
- shared fencing staging removal
- drop transactional atomic helpers and move helpers to new location
- DP/MST atomic cleanup
- Leasing cleanups and drop EXPORT_SYMBOL
- Convert drivers to atomic helpers and generic fbdev.
- removed deprecated obj_ref/unref in favour of get/put
- Improve dumb callback documentation
- MODESET_LOCK_BEGIN/END helpers
panels:
- CDTech panels, Banana Pi Panel, DLC1010GIG,
- Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA,
- Himax HX8357D, simulated RTSM AEMv8.
- GPD Win2 panel
- AUO G101EVN010
vgem:
- render node support
ttm:
- move global init out of drivers
- fix LRU handling for ghost objects
- Support for simultaneous submissions to multiple engines
scheduler:
- timeout/fault handling changes to help GPU recovery
- helpers for hw with preemption support
i915:
- Scaler/Watermark fixes
- DP MST + powerwell fixes
- PSR fixes
- Break long get/put shmemfs pages
- Icelake fixes
- Icelake DSI video mode enablement
- Engine workaround improvements
amdgpu:
- freesync support
- GPU reset enabled on CI, VI, SOC15 dGPUs
- ABM support in DC
- KFD support for vega12/polaris12
- SDMA paging queue on vega
- More amdkfd code sharing
- DCC scanout on GFX9
- DC kerneldoc
- Updated SMU firmware for GFX8 chips
- XGMI PSP + hive reset support
- GPU reset
- DC trace support
- Powerplay updates for newer Polaris
- Cursor plane update fast path
- kfd dma-buf support
virtio-gpu:
- add EDID support
vmwgfx:
- pageflip with damage support
nouveau:
- Initial Turing TU104/TU106 modesetting support
msm:
- a2xx gpu support for apq8060 and imx5
- a2xx gpummu support
- mdp4 display support for apq8060
- DPU fixes and cleanups
- enhanced profiling support
- debug object naming interface
- get_iova/page pinning decoupling
tegra:
- Tegra194 host1x, VIC and display support enabled
- Audio over HDMI for Tegra186 and Tegra194
exynos:
- DMA/IOMMU refactoring
- plane alpha + blend mode support
- Color format fixes for mixer driver
rcar-du:
- R8A7744 and R8A77470 support
- R8A77965 LVDS support
imx:
- fbdev emulation fix
- multi-tiled scalling fixes
- SPDX identifiers
rockchip
- dw_hdmi support
- dw-mipi-dsi + dual dsi support
- mailbox read size fix
qxl:
- fix cursor pinning
vc4:
- YUV support (scaling + cursor)
v3d:
- enable TFU (Texture Formatting Unit)
mali-dp:
- add support for linear tiled formats
sun4i:
- Display Engine 3 support
- H6 DE3 mixer 0 support
- H6 display engine support
- dw-hdmi support
- H6 HDMI phy support
- implicit fence waiting
- BGRX8888 support
meson:
- Overlay plane support
- implicit fence waiting
- HDMI 1.4 4k modes
bridge:
- i2c fixes for sii902x"
* tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits)
drm/amd/display: Add fast path for cursor plane updates
drm/amdgpu: Enable GPU recovery by default for CI
drm/amd/display: Fix duplicating scaling/underscan connector state
drm/amd/display: Fix unintialized max_bpc state values
Revert "drm/amd/display: Set RMX_ASPECT as default"
drm/amdgpu: Fix stub function name
drm/msm/dpu: Fix clock issue after bind failure
drm/msm/dpu: Clean up dpu_media_info.h static inline functions
drm/msm/dpu: Further cleanups for static inline functions
drm/msm/dpu: Cleanup the debugfs functions
drm/msm/dpu: Remove dpu_irq and unused functions
drm/msm: Make irq_postinstall optional
drm/msm/dpu: Cleanup callers of dpu_hw_blk_init
drm/msm/dpu: Remove unused functions
drm/msm/dpu: Remove dpu_crtc_is_enabled()
drm/msm/dpu: Remove dpu_crtc_get_mixer_height
drm/msm/dpu: Remove dpu_dbg
drm/msm: dpu: Remove crtc_lock
drm/msm: dpu: Remove vblank_requested flag from dpu_crtc
drm/msm: dpu: Separate crtc assignment from vblank enable
...
2018-12-26 02:48:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
|
2018-10-11 04:11:16 +07:00
|
|
|
priv->event_thread[i].thread = NULL;
|
|
|
|
goto err_msm_uninit;
|
|
|
|
}
|
|
|
|
|
2018-06-28 02:26:09 +07:00
|
|
|
ret = sched_setscheduler(priv->event_thread[i].thread,
|
2018-10-11 04:11:16 +07:00
|
|
|
SCHED_FIFO, ¶m);
|
2018-06-28 02:26:09 +07:00
|
|
|
if (ret)
|
2018-10-11 04:11:16 +07:00
|
|
|
dev_warn(dev, "event_thread set priority failed:%d\n",
|
|
|
|
ret);
|
2018-06-28 02:26:09 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ret = drm_vblank_init(ddev, priv->num_crtcs);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
if (ret < 0) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2016-05-18 16:36:03 +07:00
|
|
|
if (kms) {
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
ret = drm_irq_install(ddev, kms->irq);
|
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
if (ret < 0) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
2016-05-18 16:36:03 +07:00
|
|
|
}
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ret = drm_dev_register(ddev, 0);
|
|
|
|
if (ret)
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
2016-05-02 12:35:54 +07:00
|
|
|
|
|
|
|
drm_mode_config_reset(ddev);
|
2014-11-09 01:21:06 +07:00
|
|
|
|
2015-07-13 13:42:07 +07:00
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
2018-12-04 22:16:58 +07:00
|
|
|
if (kms && fbdev)
|
2016-05-02 12:35:54 +07:00
|
|
|
priv->fbdev = msm_fbdev_init(ddev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
#endif
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
ret = msm_debugfs_late_init(ddev);
|
2014-05-31 01:47:38 +07:00
|
|
|
if (ret)
|
2018-06-28 01:35:28 +07:00
|
|
|
goto err_msm_uninit;
|
2014-05-31 01:47:38 +07:00
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
drm_kms_helper_poll_init(ddev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2018-06-28 01:35:28 +07:00
|
|
|
err_msm_uninit:
|
2016-05-02 12:35:54 +07:00
|
|
|
msm_drm_uninit(dev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
return ret;
|
2018-06-28 01:35:28 +07:00
|
|
|
err_destroy_mdss:
|
|
|
|
if (mdss && mdss->funcs)
|
|
|
|
mdss->funcs->destroy(ddev);
|
|
|
|
err_free_priv:
|
|
|
|
kfree(priv);
|
2018-09-26 18:48:59 +07:00
|
|
|
err_put_drm_dev:
|
|
|
|
drm_dev_put(ddev);
|
2018-06-28 01:35:28 +07:00
|
|
|
return ret;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 12:35:54 +07:00
|
|
|
/*
|
|
|
|
* DRM operations:
|
|
|
|
*/
|
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
static void load_gpu(struct drm_device *dev)
|
|
|
|
{
|
2014-07-11 22:59:22 +07:00
|
|
|
static DEFINE_MUTEX(init_lock);
|
2013-07-19 23:59:32 +07:00
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
|
2014-07-11 22:59:22 +07:00
|
|
|
mutex_lock(&init_lock);
|
|
|
|
|
2014-09-06 00:30:27 +07:00
|
|
|
if (!priv->gpu)
|
|
|
|
priv->gpu = adreno_load_gpu(dev);
|
2013-07-19 23:59:32 +07:00
|
|
|
|
2014-07-11 22:59:22 +07:00
|
|
|
mutex_unlock(&init_lock);
|
2013-07-19 23:59:32 +07:00
|
|
|
}
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
static int context_init(struct drm_device *dev, struct drm_file *file)
|
2013-07-19 23:59:32 +07:00
|
|
|
{
|
|
|
|
struct msm_file_private *ctx;
|
|
|
|
|
|
|
|
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
|
|
|
if (!ctx)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
msm_submitqueue_init(dev, ctx);
|
2017-10-21 00:06:55 +07:00
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
file->driver_priv = ctx;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-21 00:06:55 +07:00
|
|
|
static int msm_open(struct drm_device *dev, struct drm_file *file)
|
|
|
|
{
|
|
|
|
/* For now, load gpu on open.. to avoid the requirement of having
|
|
|
|
* firmware in the initrd.
|
|
|
|
*/
|
|
|
|
load_gpu(dev);
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
return context_init(dev, file);
|
2017-10-21 00:06:55 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void context_close(struct msm_file_private *ctx)
|
|
|
|
{
|
|
|
|
msm_submitqueue_close(ctx);
|
|
|
|
kfree(ctx);
|
|
|
|
}
|
|
|
|
|
2017-03-08 21:12:46 +07:00
|
|
|
static void msm_postclose(struct drm_device *dev, struct drm_file *file)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2013-07-19 23:59:32 +07:00
|
|
|
struct msm_file_private *ctx = file->driver_priv;
|
|
|
|
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
if (ctx == priv->lastctx)
|
|
|
|
priv->lastctx = NULL;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2017-10-21 00:06:55 +07:00
|
|
|
context_close(ctx);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2013-12-11 17:34:42 +07:00
|
|
|
static irqreturn_t msm_irq(int irq, void *arg)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
|
|
|
struct drm_device *dev = arg;
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
return kms->funcs->irq(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
kms->funcs->irq_preinstall(kms);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
2018-12-04 05:47:19 +07:00
|
|
|
|
|
|
|
if (kms->funcs->irq_postinstall)
|
|
|
|
return kms->funcs->irq_postinstall(kms);
|
|
|
|
|
|
|
|
return 0;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
BUG_ON(!kms);
|
|
|
|
kms->funcs->irq_uninstall(kms);
|
|
|
|
}
|
|
|
|
|
2015-09-24 23:35:31 +07:00
|
|
|
static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
if (!kms)
|
|
|
|
return -ENXIO;
|
2015-09-24 23:35:31 +07:00
|
|
|
DBG("dev=%p, crtc=%u", dev, pipe);
|
|
|
|
return vblank_ctrl_queue_work(priv, pipe, true);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2015-09-24 23:35:31 +07:00
|
|
|
static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct msm_kms *kms = priv->kms;
|
|
|
|
if (!kms)
|
|
|
|
return;
|
2015-09-24 23:35:31 +07:00
|
|
|
DBG("dev=%p, crtc=%u", dev, pipe);
|
|
|
|
vblank_ctrl_queue_work(priv, pipe, false);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
/*
|
|
|
|
* DRM ioctls:
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int msm_ioctl_get_param(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
struct drm_msm_param *args = data;
|
|
|
|
struct msm_gpu *gpu;
|
|
|
|
|
|
|
|
/* for now, we just have 3d pipe.. eventually this would need to
|
|
|
|
* be more clever to dispatch to appropriate gpu module:
|
|
|
|
*/
|
|
|
|
if (args->pipe != MSM_PIPE_3D0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
gpu = priv->gpu;
|
|
|
|
|
|
|
|
if (!gpu)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
return gpu->funcs->get_param(gpu, args->param, &args->value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_new *args = data;
|
2014-03-03 21:42:33 +07:00
|
|
|
|
|
|
|
if (args->flags & ~MSM_BO_FLAGS) {
|
|
|
|
DRM_ERROR("invalid flags: %08x\n", args->flags);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
return msm_gem_new_handle(dev, file, args->size,
|
2018-11-08 05:35:52 +07:00
|
|
|
args->flags, &args->handle, NULL);
|
2013-07-19 23:59:32 +07:00
|
|
|
}
|
|
|
|
|
2015-05-11 22:50:03 +07:00
|
|
|
static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
|
|
|
|
{
|
|
|
|
return ktime_set(timeout.tv_sec, timeout.tv_nsec);
|
|
|
|
}
|
2013-07-19 23:59:32 +07:00
|
|
|
|
|
|
|
static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_cpu_prep *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
2015-05-11 22:50:03 +07:00
|
|
|
ktime_t timeout = to_ktime(args->timeout);
|
2013-07-19 23:59:32 +07:00
|
|
|
int ret;
|
|
|
|
|
2014-03-03 21:42:33 +07:00
|
|
|
if (args->op & ~MSM_PREP_FLAGS) {
|
|
|
|
DRM_ERROR("invalid op: %08x\n", args->op);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2016-05-09 17:04:54 +07:00
|
|
|
obj = drm_gem_object_lookup(file, args->handle);
|
2013-07-19 23:59:32 +07:00
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
2015-05-11 22:50:03 +07:00
|
|
|
ret = msm_gem_cpu_prep(obj, args->op, &timeout);
|
2013-07-19 23:59:32 +07:00
|
|
|
|
2018-01-26 10:55:54 +07:00
|
|
|
drm_gem_object_put_unlocked(obj);
|
2013-07-19 23:59:32 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_cpu_fini *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
int ret;
|
|
|
|
|
2016-05-09 17:04:54 +07:00
|
|
|
obj = drm_gem_object_lookup(file, args->handle);
|
2013-07-19 23:59:32 +07:00
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
ret = msm_gem_cpu_fini(obj);
|
|
|
|
|
2018-01-26 10:55:54 +07:00
|
|
|
drm_gem_object_put_unlocked(obj);
|
2013-07-19 23:59:32 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-05-09 03:35:01 +07:00
|
|
|
static int msm_ioctl_gem_info_iova(struct drm_device *dev,
|
|
|
|
struct drm_gem_object *obj, uint64_t *iova)
|
|
|
|
{
|
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!priv->gpu)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2018-11-08 05:35:50 +07:00
|
|
|
/*
|
|
|
|
* Don't pin the memory here - just get an address so that userspace can
|
|
|
|
* be productive
|
|
|
|
*/
|
2017-06-13 22:07:08 +07:00
|
|
|
return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
|
2017-05-09 03:35:01 +07:00
|
|
|
}
|
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_info *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
2018-11-29 22:27:22 +07:00
|
|
|
struct msm_gem_object *msm_obj;
|
|
|
|
int i, ret = 0;
|
2013-07-19 23:59:32 +07:00
|
|
|
|
2018-11-29 21:54:42 +07:00
|
|
|
if (args->pad)
|
2013-07-19 23:59:32 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2018-11-29 21:54:42 +07:00
|
|
|
switch (args->info) {
|
|
|
|
case MSM_INFO_GET_OFFSET:
|
|
|
|
case MSM_INFO_GET_IOVA:
|
|
|
|
/* value returned as immediate, not pointer, so len==0: */
|
|
|
|
if (args->len)
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
2018-11-29 22:27:22 +07:00
|
|
|
case MSM_INFO_SET_NAME:
|
|
|
|
case MSM_INFO_GET_NAME:
|
|
|
|
break;
|
2018-11-29 21:54:42 +07:00
|
|
|
default:
|
2013-07-19 23:59:32 +07:00
|
|
|
return -EINVAL;
|
2018-11-29 21:54:42 +07:00
|
|
|
}
|
2013-07-19 23:59:32 +07:00
|
|
|
|
2016-05-09 17:04:54 +07:00
|
|
|
obj = drm_gem_object_lookup(file, args->handle);
|
2013-07-19 23:59:32 +07:00
|
|
|
if (!obj)
|
|
|
|
return -ENOENT;
|
|
|
|
|
2018-11-29 22:27:22 +07:00
|
|
|
msm_obj = to_msm_bo(obj);
|
2017-05-09 03:35:01 +07:00
|
|
|
|
2018-11-29 21:54:42 +07:00
|
|
|
switch (args->info) {
|
|
|
|
case MSM_INFO_GET_OFFSET:
|
|
|
|
args->value = msm_gem_mmap_offset(obj);
|
|
|
|
break;
|
|
|
|
case MSM_INFO_GET_IOVA:
|
|
|
|
ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
|
|
|
|
break;
|
2018-11-29 22:27:22 +07:00
|
|
|
case MSM_INFO_SET_NAME:
|
|
|
|
/* length check should leave room for terminating null: */
|
|
|
|
if (args->len >= sizeof(msm_obj->name)) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ret = copy_from_user(msm_obj->name,
|
|
|
|
u64_to_user_ptr(args->value), args->len);
|
|
|
|
msm_obj->name[args->len] = '\0';
|
|
|
|
for (i = 0; i < args->len; i++) {
|
|
|
|
if (!isprint(msm_obj->name[i])) {
|
|
|
|
msm_obj->name[i] = '\0';
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSM_INFO_GET_NAME:
|
|
|
|
if (args->value && (args->len < strlen(msm_obj->name))) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
args->len = strlen(msm_obj->name);
|
|
|
|
if (args->value) {
|
|
|
|
ret = copy_to_user(u64_to_user_ptr(args->value),
|
|
|
|
msm_obj->name, args->len);
|
|
|
|
}
|
|
|
|
break;
|
2017-05-09 03:35:01 +07:00
|
|
|
}
|
2013-07-19 23:59:32 +07:00
|
|
|
|
2018-01-26 10:55:54 +07:00
|
|
|
drm_gem_object_put_unlocked(obj);
|
2013-07-19 23:59:32 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
2016-03-16 04:22:13 +07:00
|
|
|
struct msm_drm_private *priv = dev->dev_private;
|
2013-07-19 23:59:32 +07:00
|
|
|
struct drm_msm_wait_fence *args = data;
|
2015-05-11 22:50:03 +07:00
|
|
|
ktime_t timeout = to_ktime(args->timeout);
|
2017-10-21 00:06:57 +07:00
|
|
|
struct msm_gpu_submitqueue *queue;
|
|
|
|
struct msm_gpu *gpu = priv->gpu;
|
|
|
|
int ret;
|
2014-03-03 21:42:33 +07:00
|
|
|
|
|
|
|
if (args->pad) {
|
|
|
|
DRM_ERROR("invalid pad: %08x\n", args->pad);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
if (!gpu)
|
2016-03-16 04:22:13 +07:00
|
|
|
return 0;
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
queue = msm_submitqueue_get(file->driver_priv, args->queueid);
|
|
|
|
if (!queue)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
|
|
|
|
true);
|
|
|
|
|
|
|
|
msm_submitqueue_put(queue);
|
|
|
|
return ret;
|
2013-07-19 23:59:32 +07:00
|
|
|
}
|
|
|
|
|
2016-05-18 02:44:49 +07:00
|
|
|
static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_gem_madvise *args = data;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (args->madv) {
|
|
|
|
case MSM_MADV_DONTNEED:
|
|
|
|
case MSM_MADV_WILLNEED:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
obj = drm_gem_object_lookup(file, args->handle);
|
|
|
|
if (!obj) {
|
|
|
|
ret = -ENOENT;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = msm_gem_madvise(obj, args->madv);
|
|
|
|
if (ret >= 0) {
|
|
|
|
args->retained = ret;
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
|
2018-01-26 10:55:54 +07:00
|
|
|
drm_gem_object_put(obj);
|
2016-05-18 02:44:49 +07:00
|
|
|
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-10-21 00:06:55 +07:00
|
|
|
|
|
|
|
static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
struct drm_msm_submitqueue *args = data;
|
|
|
|
|
|
|
|
if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-10-21 00:06:57 +07:00
|
|
|
return msm_submitqueue_create(dev, file->driver_priv, args->prio,
|
2017-10-21 00:06:55 +07:00
|
|
|
args->flags, &args->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file)
|
|
|
|
{
|
|
|
|
u32 id = *(u32 *) data;
|
|
|
|
|
|
|
|
return msm_submitqueue_remove(file->driver_priv, id);
|
|
|
|
}
|
|
|
|
|
2013-07-19 23:59:32 +07:00
|
|
|
static const struct drm_ioctl_desc msm_ioctls[] = {
|
2015-09-08 18:56:30 +07:00
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
|
2016-05-18 02:44:49 +07:00
|
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
|
2017-10-21 00:06:55 +07:00
|
|
|
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
|
2013-07-19 23:59:32 +07:00
|
|
|
};
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
static const struct vm_operations_struct vm_ops = {
|
|
|
|
.fault = msm_gem_fault,
|
|
|
|
.open = drm_gem_vm_open,
|
|
|
|
.close = drm_gem_vm_close,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct file_operations fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = drm_open,
|
|
|
|
.release = drm_release,
|
|
|
|
.unlocked_ioctl = drm_ioctl,
|
|
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
|
|
.poll = drm_poll,
|
|
|
|
.read = drm_read,
|
|
|
|
.llseek = no_llseek,
|
|
|
|
.mmap = msm_gem_mmap,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct drm_driver msm_driver = {
|
2013-09-28 22:28:35 +07:00
|
|
|
.driver_features = DRIVER_HAVE_IRQ |
|
|
|
|
DRIVER_GEM |
|
|
|
|
DRIVER_PRIME |
|
2013-09-28 23:01:25 +07:00
|
|
|
DRIVER_RENDER |
|
2015-06-04 21:12:22 +07:00
|
|
|
DRIVER_ATOMIC |
|
2013-09-28 22:28:35 +07:00
|
|
|
DRIVER_MODESET,
|
2013-07-19 23:59:32 +07:00
|
|
|
.open = msm_open,
|
2017-03-08 21:12:46 +07:00
|
|
|
.postclose = msm_postclose,
|
2017-12-06 01:24:59 +07:00
|
|
|
.lastclose = drm_fb_helper_lastclose,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
.irq_handler = msm_irq,
|
|
|
|
.irq_preinstall = msm_irq_preinstall,
|
|
|
|
.irq_postinstall = msm_irq_postinstall,
|
|
|
|
.irq_uninstall = msm_irq_uninstall,
|
|
|
|
.enable_vblank = msm_enable_vblank,
|
|
|
|
.disable_vblank = msm_disable_vblank,
|
|
|
|
.gem_free_object = msm_gem_free_object,
|
|
|
|
.gem_vm_ops = &vm_ops,
|
|
|
|
.dumb_create = msm_gem_dumb_create,
|
|
|
|
.dumb_map_offset = msm_gem_dumb_map_offset,
|
2013-09-28 22:28:35 +07:00
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
|
|
.gem_prime_export = drm_gem_prime_export,
|
|
|
|
.gem_prime_import = drm_gem_prime_import,
|
2017-04-13 02:11:58 +07:00
|
|
|
.gem_prime_res_obj = msm_gem_prime_res_obj,
|
2013-09-28 22:28:35 +07:00
|
|
|
.gem_prime_pin = msm_gem_prime_pin,
|
|
|
|
.gem_prime_unpin = msm_gem_prime_unpin,
|
|
|
|
.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
|
|
|
|
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
|
|
|
|
.gem_prime_vmap = msm_gem_prime_vmap,
|
|
|
|
.gem_prime_vunmap = msm_gem_prime_vunmap,
|
2014-11-12 18:38:14 +07:00
|
|
|
.gem_prime_mmap = msm_gem_prime_mmap,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
.debugfs_init = msm_debugfs_init,
|
|
|
|
#endif
|
2013-07-19 23:59:32 +07:00
|
|
|
.ioctls = msm_ioctls,
|
2017-05-09 03:34:59 +07:00
|
|
|
.num_ioctls = ARRAY_SIZE(msm_ioctls),
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
.fops = &fops,
|
|
|
|
.name = "msm",
|
|
|
|
.desc = "MSM Snapdragon DRM",
|
|
|
|
.date = "20130625",
|
2016-06-02 01:02:02 +07:00
|
|
|
.major = MSM_VERSION_MAJOR,
|
|
|
|
.minor = MSM_VERSION_MINOR,
|
|
|
|
.patchlevel = MSM_VERSION_PATCHLEVEL,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int msm_pm_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
2018-05-29 02:53:38 +07:00
|
|
|
struct msm_drm_private *priv = ddev->dev_private;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-10-06 04:04:01 +07:00
|
|
|
if (WARN_ON(priv->pm_state))
|
|
|
|
drm_atomic_state_put(priv->pm_state);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-05-29 02:53:38 +07:00
|
|
|
priv->pm_state = drm_atomic_helper_suspend(ddev);
|
|
|
|
if (IS_ERR(priv->pm_state)) {
|
2018-10-06 04:04:01 +07:00
|
|
|
int ret = PTR_ERR(priv->pm_state);
|
|
|
|
DRM_ERROR("Failed to suspend dpu, %d\n", ret);
|
|
|
|
return ret;
|
2018-05-29 02:53:38 +07:00
|
|
|
}
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_pm_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
2018-05-29 02:53:38 +07:00
|
|
|
struct msm_drm_private *priv = ddev->dev_private;
|
2018-10-06 04:04:01 +07:00
|
|
|
int ret;
|
2018-06-28 02:24:17 +07:00
|
|
|
|
2018-10-06 04:04:01 +07:00
|
|
|
if (WARN_ON(!priv->pm_state))
|
|
|
|
return -ENOENT;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-10-06 04:04:01 +07:00
|
|
|
ret = drm_atomic_helper_resume(ddev, priv->pm_state);
|
|
|
|
if (!ret)
|
|
|
|
priv->pm_state = NULL;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
2018-10-06 04:04:01 +07:00
|
|
|
return ret;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int msm_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
struct msm_drm_private *priv = ddev->dev_private;
|
2018-06-22 03:06:10 +07:00
|
|
|
struct msm_mdss *mdss = priv->mdss;
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
|
|
|
|
DBG("");
|
|
|
|
|
2018-06-22 03:06:10 +07:00
|
|
|
if (mdss && mdss->funcs)
|
|
|
|
return mdss->funcs->disable(mdss);
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
struct msm_drm_private *priv = ddev->dev_private;
|
2018-06-22 03:06:10 +07:00
|
|
|
struct msm_mdss *mdss = priv->mdss;
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
|
|
|
|
DBG("");
|
|
|
|
|
2018-06-22 03:06:10 +07:00
|
|
|
if (mdss && mdss->funcs)
|
|
|
|
return mdss->funcs->enable(mdss);
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
static const struct dev_pm_ops msm_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
|
drm/msm/mdp5: Set up runtime PM for MDSS
MDSS represents the top level wrapper that contains MDP5, DSI, HDMI and
other sub-blocks. W.r.t device heirarchy, it's the parent of all these
devices. The power domain of this device is actually tied to the GDSC
hw. When any sub-device enables its PD, MDSS's PD is also enabled.
The suspend/resume ops enable the top level clocks that end at the MDSS
boundary. For now, we're letting them all be optional, since the child
devices anyway hold a ref to these clocks.
Until now, we'd called a runtime_get() during probe, which ensured that
the GDSC was always on. Now that we've set up runtime PM for the children
devices, we can get rid of this hack.
Note: that the MDSS device is the platform_device in msm_drv.c. The
msm_runtime_suspend/resume ops call the funcs that enable/disable
the top level MDSS clocks. This is different from MDP4, where the
platform device created in msm_drv.c represents MDP4 itself. It would
have been nicer to hide these differences by adding new kms funcs, but
runtime PM needs to be enabled before kms is set up (i.e, msm_kms_init
is called).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-07-28 17:47:07 +07:00
|
|
|
SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
};
|
|
|
|
|
2014-03-04 02:19:12 +07:00
|
|
|
/*
|
|
|
|
* Componentized driver support:
|
|
|
|
*/
|
|
|
|
|
2015-11-18 13:45:14 +07:00
|
|
|
/*
|
|
|
|
* NOTE: duplication of the same code as exynos or imx (or probably any other).
|
|
|
|
* so probably some room for some helpers
|
2014-03-04 02:19:12 +07:00
|
|
|
*/
|
|
|
|
static int compare_of(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
return dev->of_node == data;
|
|
|
|
}
|
2013-12-16 04:23:05 +07:00
|
|
|
|
2016-05-19 12:08:39 +07:00
|
|
|
/*
|
|
|
|
* Identify what components need to be added by parsing what remote-endpoints
|
|
|
|
* our MDP output ports are connected to. In the case of LVDS on MDP4, there
|
|
|
|
* is no external component that we need to add since LVDS is within MDP4
|
|
|
|
* itself.
|
|
|
|
*/
|
|
|
|
static int add_components_mdp(struct device *mdp_dev,
|
|
|
|
struct component_match **matchptr)
|
|
|
|
{
|
|
|
|
struct device_node *np = mdp_dev->of_node;
|
|
|
|
struct device_node *ep_node;
|
2016-06-06 15:15:34 +07:00
|
|
|
struct device *master_dev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* on MDP4 based platforms, the MDP platform device is the component
|
|
|
|
* master that adds other display interface components to itself.
|
|
|
|
*
|
|
|
|
* on MDP5 based platforms, the MDSS platform device is the component
|
|
|
|
* master that adds MDP5 and other display interface components to
|
|
|
|
* itself.
|
|
|
|
*/
|
|
|
|
if (of_device_is_compatible(np, "qcom,mdp4"))
|
|
|
|
master_dev = mdp_dev;
|
|
|
|
else
|
|
|
|
master_dev = mdp_dev->parent;
|
2016-05-19 12:08:39 +07:00
|
|
|
|
|
|
|
for_each_endpoint_of_node(np, ep_node) {
|
|
|
|
struct device_node *intf;
|
|
|
|
struct of_endpoint ep;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = of_graph_parse_endpoint(ep_node, &ep);
|
|
|
|
if (ret) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
|
2016-05-19 12:08:39 +07:00
|
|
|
of_node_put(ep_node);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The LCDC/LVDS port on MDP4 is a speacial case where the
|
|
|
|
* remote-endpoint isn't a component that we need to add
|
|
|
|
*/
|
|
|
|
if (of_device_is_compatible(np, "qcom,mdp4") &&
|
2016-11-17 13:42:03 +07:00
|
|
|
ep.port == 0)
|
2016-05-19 12:08:39 +07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It's okay if some of the ports don't have a remote endpoint
|
|
|
|
* specified. It just means that the port isn't connected to
|
|
|
|
* any external interface.
|
|
|
|
*/
|
|
|
|
intf = of_graph_get_remote_port_parent(ep_node);
|
2016-11-17 13:42:03 +07:00
|
|
|
if (!intf)
|
2016-05-19 12:08:39 +07:00
|
|
|
continue;
|
|
|
|
|
2018-12-05 01:04:41 +07:00
|
|
|
if (of_device_is_available(intf))
|
|
|
|
drm_of_component_match_add(master_dev, matchptr,
|
|
|
|
compare_of, intf);
|
|
|
|
|
2016-05-19 12:08:39 +07:00
|
|
|
of_node_put(intf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-06 15:15:34 +07:00
|
|
|
static int compare_name_mdp(struct device *dev, void *data)
|
|
|
|
{
|
|
|
|
return (strstr(dev_name(dev), "mdp") != NULL);
|
|
|
|
}
|
|
|
|
|
2016-05-19 12:03:57 +07:00
|
|
|
static int add_display_components(struct device *dev,
|
|
|
|
struct component_match **matchptr)
|
|
|
|
{
|
2016-06-06 15:15:34 +07:00
|
|
|
struct device *mdp_dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
2018-06-28 02:26:09 +07:00
|
|
|
* MDP5/DPU based devices don't have a flat hierarchy. There is a top
|
|
|
|
* level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
|
|
|
|
* Populate the children devices, find the MDP5/DPU node, and then add
|
|
|
|
* the interfaces to our components list.
|
2016-06-06 15:15:34 +07:00
|
|
|
*/
|
2018-06-28 02:26:09 +07:00
|
|
|
if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
|
|
|
|
of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
|
2016-06-06 15:15:34 +07:00
|
|
|
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
|
|
|
|
if (ret) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to populate children devices\n");
|
2016-06-06 15:15:34 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
|
|
|
|
if (!mdp_dev) {
|
2018-10-21 00:49:26 +07:00
|
|
|
DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
|
2016-06-06 15:15:34 +07:00
|
|
|
of_platform_depopulate(dev);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
put_device(mdp_dev);
|
|
|
|
|
|
|
|
/* add the MDP component itself */
|
2016-10-19 17:28:27 +07:00
|
|
|
drm_of_component_match_add(dev, matchptr, compare_of,
|
|
|
|
mdp_dev->of_node);
|
2016-06-06 15:15:34 +07:00
|
|
|
} else {
|
|
|
|
/* MDP4 */
|
|
|
|
mdp_dev = dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = add_components_mdp(mdp_dev, matchptr);
|
|
|
|
if (ret)
|
|
|
|
of_platform_depopulate(dev);
|
|
|
|
|
|
|
|
return ret;
|
2016-05-19 12:03:57 +07:00
|
|
|
}
|
|
|
|
|
2016-05-19 15:03:52 +07:00
|
|
|
/*
|
|
|
|
* We don't know what's the best binding to link the gpu with the drm device.
|
|
|
|
* Fow now, we just hunt for all the possible gpus that we support, and add them
|
|
|
|
* as components.
|
|
|
|
*/
|
|
|
|
static const struct of_device_id msm_gpu_match[] = {
|
2017-01-30 23:02:27 +07:00
|
|
|
{ .compatible = "qcom,adreno" },
|
2016-05-19 15:03:52 +07:00
|
|
|
{ .compatible = "qcom,adreno-3xx" },
|
2018-12-04 22:16:58 +07:00
|
|
|
{ .compatible = "amd,imageon" },
|
2016-05-19 15:03:52 +07:00
|
|
|
{ .compatible = "qcom,kgsl-3d0" },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
2016-05-19 12:03:57 +07:00
|
|
|
static int add_gpu_components(struct device *dev,
|
|
|
|
struct component_match **matchptr)
|
|
|
|
{
|
2016-05-19 15:03:52 +07:00
|
|
|
struct device_node *np;
|
|
|
|
|
|
|
|
np = of_find_matching_node(NULL, msm_gpu_match);
|
|
|
|
if (!np)
|
|
|
|
return 0;
|
|
|
|
|
2016-10-19 17:28:27 +07:00
|
|
|
drm_of_component_match_add(dev, matchptr, compare_of, np);
|
2016-05-19 15:03:52 +07:00
|
|
|
|
|
|
|
of_node_put(np);
|
|
|
|
|
|
|
|
return 0;
|
2016-05-19 12:03:57 +07:00
|
|
|
}
|
|
|
|
|
2014-04-19 17:20:42 +07:00
|
|
|
static int msm_drm_bind(struct device *dev)
|
|
|
|
{
|
2016-05-02 12:35:54 +07:00
|
|
|
return msm_drm_init(dev, &msm_driver);
|
2014-04-19 17:20:42 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void msm_drm_unbind(struct device *dev)
|
|
|
|
{
|
2016-05-02 12:35:54 +07:00
|
|
|
msm_drm_uninit(dev);
|
2014-04-19 17:20:42 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct component_master_ops msm_drm_ops = {
|
|
|
|
.bind = msm_drm_bind,
|
|
|
|
.unbind = msm_drm_unbind,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Platform driver:
|
|
|
|
*/
|
2014-03-04 02:19:12 +07:00
|
|
|
|
2014-04-19 17:20:42 +07:00
|
|
|
static int msm_pdev_probe(struct platform_device *pdev)
|
2014-03-04 02:19:12 +07:00
|
|
|
{
|
2014-04-19 17:20:42 +07:00
|
|
|
struct component_match *match = NULL;
|
2016-05-19 12:03:57 +07:00
|
|
|
int ret;
|
|
|
|
|
2018-12-04 22:16:58 +07:00
|
|
|
if (get_mdp_ver(pdev)) {
|
|
|
|
ret = add_display_components(&pdev->dev, &match);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2015-11-18 13:45:14 +07:00
|
|
|
|
2016-05-19 12:03:57 +07:00
|
|
|
ret = add_gpu_components(&pdev->dev, &match);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-03-04 02:19:12 +07:00
|
|
|
|
2016-11-08 01:31:30 +07:00
|
|
|
/* on all devices that I am aware of, iommu's which can map
|
|
|
|
* any address the cpu can see are used:
|
|
|
|
*/
|
|
|
|
ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-04-19 17:20:42 +07:00
|
|
|
return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int msm_pdev_remove(struct platform_device *pdev)
|
|
|
|
{
|
2014-03-04 02:19:12 +07:00
|
|
|
component_master_del(&pdev->dev, &msm_drm_ops);
|
2016-06-06 15:15:34 +07:00
|
|
|
of_platform_depopulate(&pdev->dev);
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
static const struct of_device_id dt_match[] = {
|
2018-06-28 01:26:24 +07:00
|
|
|
{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
|
|
|
|
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
|
2018-06-28 02:26:09 +07:00
|
|
|
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, dt_match);
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
static struct platform_driver msm_platform_driver = {
|
|
|
|
.probe = msm_pdev_probe,
|
|
|
|
.remove = msm_pdev_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "msm",
|
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-12-01 05:51:47 +07:00
|
|
|
.of_match_table = dt_match,
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
.pm = &msm_pm_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init msm_drm_register(void)
|
|
|
|
{
|
2017-07-07 03:33:44 +07:00
|
|
|
if (!modeset)
|
|
|
|
return -EINVAL;
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
DBG("init");
|
drm/msm/mdp5: Create a separate MDP5 device
In order to have a tree-like device hierarchy between MDSS and its
sub-blocks (MDP5, DSI, HDMI, eDP etc), we need to create a separate
device/driver for MDP5. Currently, MDP5 and MDSS are squashed
together are are tied to the top level platform_device, which is
also the one used to create drm_device.
The mdp5_kms_init code is split into two parts. The part where device
resources are allocated are associated with the MDP5 driver's probe,
the rest is executed later when we initialize modeset.
With this change, unlike MDP4, the MDP5 platform_device isn't tied to
the top level drm_device anymore. The top level drm_device is now
associated with a platform device that corresponds to MDSS wrapper
hardware.
Create mdp5_init/destroy funcs that will be used by the MDP5 driver
probe/remove. Use the HW_VERSION register in the MDP5 register address
space. Both the MDSS and MDP VERSION registers give out identical
version info.
The older mdp5_kms_init code is left as is for now, this would be removed
later when we have all the pieces to support the new device hierarchy.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-05-30 18:06:50 +07:00
|
|
|
msm_mdp_register();
|
2018-06-28 02:26:09 +07:00
|
|
|
msm_dpu_register();
|
2015-03-27 06:25:17 +07:00
|
|
|
msm_dsi_register();
|
2014-12-13 02:41:17 +07:00
|
|
|
msm_edp_register();
|
2016-02-23 04:08:35 +07:00
|
|
|
msm_hdmi_register();
|
2014-09-06 00:06:37 +07:00
|
|
|
adreno_register();
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
return platform_driver_register(&msm_platform_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit msm_drm_unregister(void)
|
|
|
|
{
|
|
|
|
DBG("fini");
|
|
|
|
platform_driver_unregister(&msm_platform_driver);
|
2016-02-23 04:08:35 +07:00
|
|
|
msm_hdmi_unregister();
|
2014-09-06 00:06:37 +07:00
|
|
|
adreno_unregister();
|
2014-12-13 02:41:17 +07:00
|
|
|
msm_edp_unregister();
|
2015-03-27 06:25:17 +07:00
|
|
|
msm_dsi_unregister();
|
drm/msm/mdp5: Create a separate MDP5 device
In order to have a tree-like device hierarchy between MDSS and its
sub-blocks (MDP5, DSI, HDMI, eDP etc), we need to create a separate
device/driver for MDP5. Currently, MDP5 and MDSS are squashed
together are are tied to the top level platform_device, which is
also the one used to create drm_device.
The mdp5_kms_init code is split into two parts. The part where device
resources are allocated are associated with the MDP5 driver's probe,
the rest is executed later when we initialize modeset.
With this change, unlike MDP4, the MDP5 platform_device isn't tied to
the top level drm_device anymore. The top level drm_device is now
associated with a platform device that corresponds to MDSS wrapper
hardware.
Create mdp5_init/destroy funcs that will be used by the MDP5 driver
probe/remove. Use the HW_VERSION register in the MDP5 register address
space. Both the MDSS and MDP VERSION registers give out identical
version info.
The older mdp5_kms_init code is left as is for now, this would be removed
later when we have all the pieces to support the new device hierarchy.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-05-30 18:06:50 +07:00
|
|
|
msm_mdp_unregister();
|
2018-06-28 02:26:09 +07:00
|
|
|
msm_dpu_unregister();
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 23:44:06 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(msm_drm_register);
|
|
|
|
module_exit(msm_drm_unregister);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
|
|
|
|
MODULE_DESCRIPTION("MSM DRM Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|