2018-01-27 03:22:04 +07:00
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// SPDX-License-Identifier: GPL-2.0+
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2005-04-17 05:20:36 +07:00
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/*
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* CompactPCI Hot Plug Driver PCI functions
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*
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2005-05-28 03:48:52 +07:00
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* Copyright (C) 2002,2005 by SOMA Networks, Inc.
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2005-04-17 05:20:36 +07:00
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*
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* All rights reserved.
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*
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* Send feedback to <scottm@somanetworks.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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2006-10-14 10:05:19 +07:00
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#include <linux/pci_hotplug.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/proc_fs.h>
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#include "../pci.h"
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#include "cpci_hotplug.h"
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#define MY_NAME "cpci_hotplug"
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extern int cpci_debug;
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#define dbg(format, arg...) \
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do { \
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2005-05-28 03:48:52 +07:00
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if (cpci_debug) \
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2015-12-28 04:21:11 +07:00
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printk(KERN_DEBUG "%s: " format "\n", \
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MY_NAME, ## arg); \
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2005-05-28 03:48:52 +07:00
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} while (0)
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2015-12-28 04:21:11 +07:00
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#define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
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#define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
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#define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
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2005-04-17 05:20:36 +07:00
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2014-04-19 07:13:49 +07:00
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u8 cpci_get_attention_status(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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2005-04-17 05:20:36 +07:00
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return hs_csr & 0x0008 ? 1 : 0;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_set_attention_status(struct slot *slot, int status)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (status)
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2005-04-17 05:20:36 +07:00
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hs_csr |= HS_CSR_LOO;
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2005-05-28 03:48:52 +07:00
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else
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2005-04-17 05:20:36 +07:00
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hs_csr &= ~HS_CSR_LOO;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_write_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0;
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return 1;
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}
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2014-04-19 07:13:49 +07:00
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u16 cpci_get_hs_csr(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return 0xFFFF;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0xFFFF;
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return hs_csr;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_check_and_clear_ins(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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int ins = 0;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (hs_csr & HS_CSR_INS) {
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2005-04-17 05:20:36 +07:00
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/* Clear INS (by setting it) */
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2005-05-28 03:48:52 +07:00
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if (pci_bus_write_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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hs_csr))
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2005-04-17 05:20:36 +07:00
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ins = 0;
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2005-05-28 03:48:52 +07:00
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else
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ins = 1;
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2005-04-17 05:20:36 +07:00
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}
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return ins;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_check_ext(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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int ext = 0;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return 0;
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2005-05-28 03:48:52 +07:00
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if (hs_csr & HS_CSR_EXT)
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2005-04-17 05:20:36 +07:00
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ext = 1;
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return ext;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_clear_ext(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if (hs_csr & HS_CSR_EXT) {
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2005-04-17 05:20:36 +07:00
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/* Clear EXT (by setting it) */
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2005-05-28 03:48:52 +07:00
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if (pci_bus_write_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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hs_csr))
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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}
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return 0;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_led_on(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if ((hs_csr & HS_CSR_LOO) != HS_CSR_LOO) {
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2005-04-17 05:20:36 +07:00
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hs_csr |= HS_CSR_LOO;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_write_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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hs_csr)) {
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2018-09-08 14:59:01 +07:00
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err("Could not set LOO for slot %s", slot_name(slot));
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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}
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}
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return 0;
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}
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2014-04-19 07:13:49 +07:00
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int cpci_led_off(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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int hs_cap;
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u16 hs_csr;
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hs_cap = pci_bus_find_capability(slot->bus,
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slot->devfn,
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PCI_CAP_ID_CHSWP);
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2005-05-28 03:48:52 +07:00
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if (!hs_cap)
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_read_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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2005-05-28 03:48:52 +07:00
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&hs_csr))
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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2005-05-28 03:48:52 +07:00
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if (hs_csr & HS_CSR_LOO) {
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2005-04-17 05:20:36 +07:00
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hs_csr &= ~HS_CSR_LOO;
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2005-05-28 03:48:52 +07:00
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if (pci_bus_write_config_word(slot->bus,
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2005-04-17 05:20:36 +07:00
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slot->devfn,
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hs_cap + 2,
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hs_csr)) {
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2018-09-08 14:59:01 +07:00
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err("Could not clear LOO for slot %s", slot_name(slot));
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2005-04-17 05:20:36 +07:00
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return -ENODEV;
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}
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}
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return 0;
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}
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/*
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* Device configuration functions
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*/
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2014-04-15 05:11:40 +07:00
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int cpci_configure_slot(struct slot *slot)
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2005-04-17 05:20:36 +07:00
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{
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2013-01-15 10:12:20 +07:00
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struct pci_dev *dev;
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2006-08-23 06:55:57 +07:00
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struct pci_bus *parent;
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2014-01-15 02:03:14 +07:00
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int ret = 0;
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2005-04-17 05:20:36 +07:00
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2008-03-04 10:09:46 +07:00
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dbg("%s - enter", __func__);
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2005-04-17 05:20:36 +07:00
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2014-01-15 02:03:14 +07:00
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pci_lock_rescan_remove();
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2005-05-28 03:48:52 +07:00
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if (slot->dev == NULL) {
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2005-04-17 05:20:36 +07:00
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dbg("pci_dev null, finding %02x:%02x:%x",
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slot->bus->number, PCI_SLOT(slot->devfn), PCI_FUNC(slot->devfn));
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2005-05-28 03:48:52 +07:00
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slot->dev = pci_get_slot(slot->bus, slot->devfn);
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2005-04-17 05:20:36 +07:00
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}
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/* Still NULL? Well then scan for it! */
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2005-05-28 03:48:52 +07:00
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if (slot->dev == NULL) {
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2005-04-17 05:20:36 +07:00
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int n;
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dbg("pci_dev still null");
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/*
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* This will generate pci_dev structures for all functions, but
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* we will only call this case when lookup fails.
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*/
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n = pci_scan_slot(slot->bus, slot->devfn);
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2008-03-04 10:09:46 +07:00
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dbg("%s: pci_scan_slot returned %d", __func__, n);
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2005-05-28 03:48:52 +07:00
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slot->dev = pci_get_slot(slot->bus, slot->devfn);
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if (slot->dev == NULL) {
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2005-04-17 05:20:36 +07:00
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err("Could not find PCI device for slot %02x", slot->number);
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2014-01-15 02:03:14 +07:00
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ret = -ENODEV;
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goto out;
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2005-04-17 05:20:36 +07:00
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}
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}
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2006-08-23 06:55:57 +07:00
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parent = slot->dev->bus;
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2017-10-21 03:38:54 +07:00
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for_each_pci_bridge(dev, parent) {
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if (PCI_SLOT(dev->devfn) == PCI_SLOT(slot->devfn))
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2012-05-18 08:58:41 +07:00
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pci_hp_add_bridge(dev);
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2015-02-25 20:23:22 +07:00
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}
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2013-01-15 10:12:20 +07:00
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2012-05-18 08:58:41 +07:00
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pci_assign_unassigned_bridge_resources(parent->self);
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2006-08-23 06:55:57 +07:00
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pci_bus_add_devices(parent);
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2005-05-10 04:31:50 +07:00
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2014-01-15 02:03:14 +07:00
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out:
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pci_unlock_rescan_remove();
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2008-03-04 10:09:46 +07:00
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dbg("%s - exit", __func__);
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2014-01-15 02:03:14 +07:00
|
|
|
return ret;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
int cpci_unconfigure_slot(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-01-15 10:12:20 +07:00
|
|
|
struct pci_dev *dev, *temp;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-03-04 10:09:46 +07:00
|
|
|
dbg("%s - enter", __func__);
|
2005-05-28 03:48:52 +07:00
|
|
|
if (!slot->dev) {
|
2005-04-17 05:20:36 +07:00
|
|
|
err("No device for slot %02x\n", slot->number);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2014-01-15 02:03:14 +07:00
|
|
|
pci_lock_rescan_remove();
|
|
|
|
|
2013-01-15 10:12:20 +07:00
|
|
|
list_for_each_entry_safe(dev, temp, &slot->bus->devices, bus_list) {
|
|
|
|
if (PCI_SLOT(dev->devfn) != PCI_SLOT(slot->devfn))
|
|
|
|
continue;
|
|
|
|
pci_dev_get(dev);
|
|
|
|
pci_stop_and_remove_bus_device(dev);
|
|
|
|
pci_dev_put(dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2005-06-07 02:48:04 +07:00
|
|
|
pci_dev_put(slot->dev);
|
|
|
|
slot->dev = NULL;
|
|
|
|
|
2014-01-15 02:03:14 +07:00
|
|
|
pci_unlock_rescan_remove();
|
|
|
|
|
2008-03-04 10:09:46 +07:00
|
|
|
dbg("%s - exit", __func__);
|
2005-05-10 04:31:50 +07:00
|
|
|
return 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|