2018-10-10 18:26:48 +07:00
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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2017-07-18 22:30:47 +07:00
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _SG_SW_QM2_H_
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#define _SG_SW_QM2_H_
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2018-07-24 21:21:29 +07:00
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#include <soc/fsl/dpaa2-fd.h>
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2017-07-18 22:30:47 +07:00
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static inline void dma_to_qm_sg_one(struct dpaa2_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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dpaa2_sg_set_addr(qm_sg_ptr, dma);
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dpaa2_sg_set_format(qm_sg_ptr, dpaa2_sg_single);
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dpaa2_sg_set_final(qm_sg_ptr, false);
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dpaa2_sg_set_len(qm_sg_ptr, len);
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dpaa2_sg_set_bpid(qm_sg_ptr, 0);
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dpaa2_sg_set_offset(qm_sg_ptr, offset);
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}
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/*
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* convert scatterlist to h/w link table format
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* but does not have final bit; instead, returns last entry
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*/
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static inline struct dpaa2_sg_entry *
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2019-06-10 20:30:58 +07:00
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sg_to_qm_sg(struct scatterlist *sg, int len,
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2017-07-18 22:30:47 +07:00
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struct dpaa2_sg_entry *qm_sg_ptr, u16 offset)
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{
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2019-06-10 20:30:58 +07:00
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int ent_len;
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while (len) {
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ent_len = min_t(int, sg_dma_len(sg), len);
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dma_to_qm_sg_one(qm_sg_ptr, sg_dma_address(sg), ent_len,
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offset);
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2017-07-18 22:30:47 +07:00
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qm_sg_ptr++;
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sg = sg_next(sg);
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2019-06-10 20:30:58 +07:00
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len -= ent_len;
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2017-07-18 22:30:47 +07:00
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}
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return qm_sg_ptr - 1;
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}
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/*
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* convert scatterlist to h/w link table format
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* scatterlist must have been previously dma mapped
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*/
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2019-06-10 20:30:58 +07:00
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static inline void sg_to_qm_sg_last(struct scatterlist *sg, int len,
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2017-07-18 22:30:47 +07:00
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struct dpaa2_sg_entry *qm_sg_ptr,
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u16 offset)
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{
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2019-06-10 20:30:58 +07:00
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qm_sg_ptr = sg_to_qm_sg(sg, len, qm_sg_ptr, offset);
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2017-07-18 22:30:47 +07:00
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dpaa2_sg_set_final(qm_sg_ptr, true);
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}
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#endif /* _SG_SW_QM2_H_ */
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