2011-05-21 10:18:55 +07:00
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#
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# Marvell device configuration
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#
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config NET_VENDOR_MARVELL
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bool "Marvell devices"
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2011-08-23 15:29:52 +07:00
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default y
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2016-11-18 02:19:13 +07:00
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depends on PCI || CPU_PXA168 || MV64X60 || PPC32 || PLAT_ORION || INET || COMPILE_TEST
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2011-05-21 10:18:55 +07:00
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---help---
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2015-06-22 03:28:02 +07:00
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If you have a network (Ethernet) card belonging to this class, say Y.
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2011-05-21 10:18:55 +07:00
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Note that the answer to this question doesn't directly affect the
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kernel: saying N will just cause the configurator to skip all
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the questions about Marvell devices. If you say Y, you will be
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asked for your specific card in the following questions.
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if NET_VENDOR_MARVELL
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config MV643XX_ETH
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tristate "Marvell Discovery (643XX) and Orion ethernet support"
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2016-11-18 02:19:13 +07:00
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depends on (MV64X60 || PPC32 || PLAT_ORION || COMPILE_TEST) && INET
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depends on HAS_DMA
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2011-05-21 10:18:55 +07:00
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select PHYLIB
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2013-03-22 10:39:28 +07:00
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select MVMDIO
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2011-05-21 10:18:55 +07:00
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---help---
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This driver supports the gigabit ethernet MACs in the
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Marvell Discovery PPC/MIPS chipset family (MV643XX) and
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in the Marvell Orion ARM SoC family.
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Some boards that use the Discovery chipset are the Momenco
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Ocelot C and Jaguar ATX and Pegasos II.
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2012-11-12 23:03:47 +07:00
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config MVMDIO
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tristate "Marvell MDIO interface support"
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2014-01-14 22:45:43 +07:00
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depends on HAS_IOMEM
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net: mvmdio: add select PHYLIB
The mvmdio driver uses the phylib API, so it should select the PHYLIB
symbol, otherwise, a build with mvmdio (but without mvneta) fails to
build with undefined symbols such as mdiobus_unregister, mdiobus_free,
etc.
The mvneta driver does not use the phylib API directly, so it does not
need to select PHYLIB. It already selects the mvmdio driver anyway.
Historically, this problem is due to the fact that the PHY handling
was originally part of mvneta, and was later moved to a separate
driver, without updating the Kconfig select statements
accordingly. And since there was no functional reason to use mvmdio
without mvneta, this case was not tested.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2013-04-13 13:18:56 +07:00
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select PHYLIB
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2012-11-12 23:03:47 +07:00
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---help---
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This driver supports the MDIO interface found in the network
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interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
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Dove, Armada 370 and Armada XP).
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2013-03-22 10:39:28 +07:00
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This driver is used by the MV643XX_ETH and MVNETA drivers.
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2012-11-12 23:03:47 +07:00
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2016-03-16 04:47:14 +07:00
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config MVNETA_BM_ENABLE
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net: mvneta: bm: add support for hardware buffer management
Buffer manager (BM) is a dedicated hardware unit that can be used by all
ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
path by sparing DRAM access on refilling buffer pool, hardware-based
filling of descriptor ring data and better memory utilization due to HW
arbitration for using 'short' pools for small packets.
Tests performed with A388 SoC working as a network bridge between two
packet generators showed increase of maximum processed 64B packets by
~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
when pushing 1500B-packets with a line rate achieved, CPU load decreased
from around 25% without BM to 20% with BM.
BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
are called external BP pools - BPPE. Allocating and releasing buffer
pointers (BP) to/from BPPE is performed indirectly by write/read access
to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
BM hardware controls status of BPPE automatically, as well as assigning
proper buffers to RX descriptors. For more details please refer to
Functional Specification of Armada XP or 38x SoC.
In order to enable support for a separate hardware block, common for all
ports, a new driver has to be implemented ('mvneta_bm'). It provides
initialization sequence of address space, clocks, registers, SRAM,
empty pools' structures and also obtaining optional configuration
from DT (please refer to device tree binding documentation). mvneta_bm
exposes also a necessary API to mvneta driver, as well as a dedicated
structure with BM information (bm_priv), whose presence is used as a
flag notifying of BM usage by port. It has to be ensured that mvneta_bm
probe is executed prior to the ones in ports' driver. In case BM is not
used or its probe fails, mvneta falls back to use software buffer
management.
A sequence executed in mvneta_probe function is modified in order to have
an access to needed resources before possible port's BM initialization is
done. According to port-pools mapping provided by DT appropriate registers
are configured and the buffer pools are filled. RX path is modified
accordingly. Becaues the hardware allows a wide variety of configuration
options, following assumptions are made:
* using BM mechanisms can be selectively disabled/enabled basing
on DT configuration among the ports
* 'long' pool's single buffer size is tied to port's MTU
* using 'long' pool by port is obligatory and it cannot be shared
* using 'short' pool for smaller packets is optional
* one 'short' pool can be shared among all ports
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clement@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-14 15:39:03 +07:00
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tristate "Marvell Armada 38x/XP network interface BM support"
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depends on MVNETA
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2016-12-02 00:03:08 +07:00
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depends on !64BIT
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net: mvneta: bm: add support for hardware buffer management
Buffer manager (BM) is a dedicated hardware unit that can be used by all
ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
path by sparing DRAM access on refilling buffer pool, hardware-based
filling of descriptor ring data and better memory utilization due to HW
arbitration for using 'short' pools for small packets.
Tests performed with A388 SoC working as a network bridge between two
packet generators showed increase of maximum processed 64B packets by
~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
when pushing 1500B-packets with a line rate achieved, CPU load decreased
from around 25% without BM to 20% with BM.
BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
are called external BP pools - BPPE. Allocating and releasing buffer
pointers (BP) to/from BPPE is performed indirectly by write/read access
to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
BM hardware controls status of BPPE automatically, as well as assigning
proper buffers to RX descriptors. For more details please refer to
Functional Specification of Armada XP or 38x SoC.
In order to enable support for a separate hardware block, common for all
ports, a new driver has to be implemented ('mvneta_bm'). It provides
initialization sequence of address space, clocks, registers, SRAM,
empty pools' structures and also obtaining optional configuration
from DT (please refer to device tree binding documentation). mvneta_bm
exposes also a necessary API to mvneta driver, as well as a dedicated
structure with BM information (bm_priv), whose presence is used as a
flag notifying of BM usage by port. It has to be ensured that mvneta_bm
probe is executed prior to the ones in ports' driver. In case BM is not
used or its probe fails, mvneta falls back to use software buffer
management.
A sequence executed in mvneta_probe function is modified in order to have
an access to needed resources before possible port's BM initialization is
done. According to port-pools mapping provided by DT appropriate registers
are configured and the buffer pools are filled. RX path is modified
accordingly. Becaues the hardware allows a wide variety of configuration
options, following assumptions are made:
* using BM mechanisms can be selectively disabled/enabled basing
on DT configuration among the ports
* 'long' pool's single buffer size is tied to port's MTU
* using 'long' pool by port is obligatory and it cannot be shared
* using 'short' pool for smaller packets is optional
* one 'short' pool can be shared among all ports
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clement@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-14 15:39:03 +07:00
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---help---
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This driver supports auxiliary block of the network
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interface units in the Marvell ARMADA XP and ARMADA 38x SoC
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family, which is called buffer manager.
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This driver, when enabled, strictly cooperates with mvneta
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driver and is common for all network ports of the devices,
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even for Armada 370 SoC, which doesn't support hardware
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buffer management.
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net: mvneta: driver for Marvell Armada 370/XP network unit
This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
2012-08-17 18:04:28 +07:00
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config MVNETA
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2016-12-02 00:03:09 +07:00
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tristate "Marvell Armada 370/38x/XP/37xx network interface support"
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depends on ARCH_MVEBU || COMPILE_TEST
|
2016-11-18 02:19:13 +07:00
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depends on HAS_DMA
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net: mvneta: driver for Marvell Armada 370/XP network unit
This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
2012-08-17 18:04:28 +07:00
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select MVMDIO
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2018-01-03 00:24:44 +07:00
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select PHYLINK
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net: mvneta: driver for Marvell Armada 370/XP network unit
This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
2012-08-17 18:04:28 +07:00
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---help---
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This driver supports the network interface units in the
|
2016-12-02 00:03:09 +07:00
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Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
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ARMADA 37xx SoC family.
|
net: mvneta: driver for Marvell Armada 370/XP network unit
This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
2012-08-17 18:04:28 +07:00
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Note that this driver is distinct from the mv643xx_eth
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driver, which should be used for the older Marvell SoCs
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(Dove, Orion, Discovery, Kirkwood).
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|
2016-03-16 04:47:14 +07:00
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config MVNETA_BM
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tristate
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2016-12-02 00:03:08 +07:00
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depends on !64BIT
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2016-05-12 03:13:23 +07:00
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default y if MVNETA=y && MVNETA_BM_ENABLE!=n
|
2016-03-16 04:47:14 +07:00
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default MVNETA_BM_ENABLE
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select HWBM
|
2016-12-10 17:38:32 +07:00
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select GENERIC_ALLOCATOR
|
2016-03-16 04:47:14 +07:00
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help
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MVNETA_BM must not be 'm' if MVNETA=y, so this symbol ensures
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that all dependencies are met.
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2014-07-11 02:52:13 +07:00
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config MVPP2
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2017-03-07 22:53:20 +07:00
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tristate "Marvell Armada 375/7K/8K network interface support"
|
2017-02-21 17:28:13 +07:00
|
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|
depends on ARCH_MVEBU || COMPILE_TEST
|
2016-11-18 02:19:13 +07:00
|
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depends on HAS_DMA
|
2014-07-11 02:52:13 +07:00
|
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select MVMDIO
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|
---help---
|
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|
This driver supports the network interface units in the
|
2017-03-07 22:53:20 +07:00
|
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Marvell ARMADA 375, 7K and 8K SoCs.
|
2014-07-11 02:52:13 +07:00
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2011-05-21 10:18:55 +07:00
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config PXA168_ETH
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tristate "Marvell pxa168 ethernet support"
|
2014-10-09 21:15:42 +07:00
|
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depends on HAS_IOMEM && HAS_DMA
|
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depends on CPU_PXA168 || ARCH_BERLIN || COMPILE_TEST
|
2011-05-21 10:18:55 +07:00
|
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select PHYLIB
|
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|
---help---
|
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This driver supports the pxa168 Ethernet ports.
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To compile this driver as a module, choose M here. The module
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will be called pxa168_eth.
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config SKGE
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tristate "Marvell Yukon Gigabit Ethernet support"
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depends on PCI
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select CRC32
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---help---
|
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|
This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
|
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and related Gigabit Ethernet adapters. It is a new smaller driver
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with better performance and more complete ethtool support.
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It does not support the link failover and network management
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features that "portable" vendor supplied sk98lin driver does.
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This driver supports adapters based on the original Yukon chipset:
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Marvell 88E8001, Belkin F5D5005, CNet GigaCard, DLink DGE-530T,
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Linksys EG1032/EG1064, 3Com 3C940/3C940B, SysKonnect SK-9871/9872.
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It does not support the newer Yukon2 chipset: a separate driver,
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sky2, is provided for these adapters.
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To compile this driver as a module, choose M here: the module
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will be called skge. This is recommended.
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config SKGE_DEBUG
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bool "Debugging interface"
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depends on SKGE && DEBUG_FS
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|
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---help---
|
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|
This option adds the ability to dump driver state for debugging.
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|
The file /sys/kernel/debug/skge/ethX displays the state of the internal
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transmit and receive rings.
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If unsure, say N.
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config SKGE_GENESIS
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bool "Support for older SysKonnect Genesis boards"
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depends on SKGE
|
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|
---help---
|
|
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|
|
This enables support for the older and uncommon SysKonnect Genesis
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chips, which support MII via an external transceiver, instead of
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an internal one. Disabling this option will save some memory
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by making code smaller. If unsure say Y.
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config SKY2
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tristate "Marvell Yukon 2 support"
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depends on PCI
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select CRC32
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---help---
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This driver supports Gigabit Ethernet adapters based on the
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Marvell Yukon 2 chipset:
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Marvell 88E8021/88E8022/88E8035/88E8036/88E8038/88E8050/88E8052/
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88E8053/88E8055/88E8061/88E8062, SysKonnect SK-9E21D/SK-9S21
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There is companion driver for the older Marvell Yukon and
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SysKonnect Genesis based adapters: skge.
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To compile this driver as a module, choose M here: the module
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will be called sky2. This is recommended.
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config SKY2_DEBUG
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bool "Debugging interface"
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depends on SKY2 && DEBUG_FS
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---help---
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This option adds the ability to dump driver state for debugging.
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The file /sys/kernel/debug/sky2/ethX displays the state of the internal
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transmit and receive rings.
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If unsure, say N.
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endif # NET_VENDOR_MARVELL
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