License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 05:20:36 +07:00
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/*
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* pcic.c: MicroSPARC-IIep PCI controller support
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*
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* Copyright (C) 1998 V. Roganov and G. Raiko
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*
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* Code is derived from Ultra/PCI PSYCHO controller support, see that
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* for author info.
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*
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* Support for diverse IIep based platforms by Pete Zaitcev.
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* CP-1200 by Eric Brower.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <asm/swift.h> /* for cache flushing. */
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#include <asm/io.h>
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#include <linux/ctype.h>
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#include <linux/pci.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/interrupt.h>
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2011-07-19 02:57:46 +07:00
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#include <linux/export.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/irq.h>
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#include <asm/oplib.h>
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2006-06-24 05:53:31 +07:00
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#include <asm/prom.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/pcic.h>
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2010-01-15 16:34:28 +07:00
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#include <asm/timex.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/timer.h>
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2016-12-25 02:46:01 +07:00
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#include <linux/uaccess.h>
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2006-10-11 04:17:05 +07:00
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#include <asm/irq_regs.h>
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2005-04-17 05:20:36 +07:00
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2014-05-17 04:25:42 +07:00
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#include "kernel.h"
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2007-07-22 09:18:57 +07:00
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#include "irq.h"
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2005-04-17 05:20:36 +07:00
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/*
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* I studied different documents and many live PROMs both from 2.30
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* family and 3.xx versions. I came to the amazing conclusion: there is
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* absolutely no way to route interrupts in IIep systems relying on
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* information which PROM presents. We must hardcode interrupt routing
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* schematics. And this actually sucks. -- zaitcev 1999/05/12
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*
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* To find irq for a device we determine which routing map
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* is in effect or, in other words, on which machine we are running.
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* We use PROM name for this although other techniques may be used
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* in special cases (Gleb reports a PROMless IIep based system).
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* Once we know the map we take device configuration address and
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* find PCIC pin number where INT line goes. Then we may either program
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* preferred irq into the PCIC or supply the preexisting irq to the device.
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*/
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struct pcic_ca2irq {
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unsigned char busno; /* PCI bus number */
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unsigned char devfn; /* Configuration address */
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unsigned char pin; /* PCIC external interrupt pin */
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unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
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unsigned int force; /* Enforce preferred IRQ */
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};
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struct pcic_sn2list {
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char *sysname;
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struct pcic_ca2irq *intmap;
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int mapdim;
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};
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/*
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* JavaEngine-1 apparently has different versions.
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*
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* According to communications with Sun folks, for P2 build 501-4628-03:
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* pin 0 - parallel, audio;
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* pin 1 - Ethernet;
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* pin 2 - su;
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* pin 3 - PS/2 kbd and mouse.
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*
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* OEM manual (805-1486):
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* pin 0: Ethernet
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* pin 1: All EBus
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* pin 2: IGA (unused)
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* pin 3: Not connected
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* OEM manual says that 501-4628 & 501-4811 are the same thing,
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* only the latter has NAND flash in place.
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*
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* So far unofficial Sun wins over the OEM manual. Poor OEMs...
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*/
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static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
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{ 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
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{ 0, 0x01, 1, 6, 1 }, /* Happy Meal */
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{ 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
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};
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/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
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static struct pcic_ca2irq pcic_i_jse[] = {
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{ 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
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{ 0, 0x01, 1, 6, 0 }, /* hme */
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{ 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
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{ 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
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{ 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
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{ 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
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{ 0, 0x80, 5, 11, 0 }, /* EIDE */
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/* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
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{ 0, 0xA0, 4, 9, 0 }, /* USB */
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/*
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* Some pins belong to non-PCI devices, we hardcode them in drivers.
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* sun4m timers - irq 10, 14
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* PC style RTC - pin 7, irq 4 ?
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* Smart card, Parallel - pin 4 shared with USB, ISA
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* audio - pin 3, irq 5 ?
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*/
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};
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/* SPARCengine-6 was the original release name of CP1200.
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* The documentation differs between the two versions
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*/
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static struct pcic_ca2irq pcic_i_se6[] = {
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{ 0, 0x08, 0, 2, 0 }, /* SCSI */
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{ 0, 0x01, 1, 6, 0 }, /* HME */
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{ 0, 0x00, 3, 13, 0 }, /* EBus */
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};
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/*
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* Krups (courtesy of Varol Kaptan)
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* No documentation available, but it was easy to guess
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* because it was very similar to Espresso.
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*
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* pin 0 - kbd, mouse, serial;
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* pin 1 - Ethernet;
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* pin 2 - igs (we do not use it);
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* pin 3 - audio;
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* pin 4,5,6 - unused;
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* pin 7 - RTC (from P2 onwards as David B. says).
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*/
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static struct pcic_ca2irq pcic_i_jk[] = {
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{ 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
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{ 0, 0x01, 1, 6, 0 }, /* hme */
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};
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/*
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* Several entries in this list may point to the same routing map
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* as several PROMs may be installed on the same physical board.
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*/
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#define SN2L_INIT(name, map) \
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2005-11-10 03:03:05 +07:00
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{ name, map, ARRAY_SIZE(map) }
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2005-04-17 05:20:36 +07:00
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static struct pcic_sn2list pcic_known_sysnames[] = {
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SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
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SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
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SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
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SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
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SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
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{ NULL, NULL, 0 }
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};
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/*
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* Only one PCIC per IIep,
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* and since we have no SMP IIep, only one per system.
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*/
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static int pcic0_up;
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static struct linux_pcic pcic0;
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2005-12-06 17:44:18 +07:00
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void __iomem *pcic_regs;
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2014-05-17 04:25:42 +07:00
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static volatile int pcic_speculative;
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static volatile int pcic_trapped;
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2005-04-17 05:20:36 +07:00
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2011-04-18 18:25:44 +07:00
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/* forward */
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unsigned int pcic_build_device_irq(struct platform_device *op,
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unsigned int real_irq);
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2005-04-17 05:20:36 +07:00
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#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
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static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
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int where, u32 *value)
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{
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struct linux_pcic *pcic;
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unsigned long flags;
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pcic = &pcic0;
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local_irq_save(flags);
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#if 0 /* does not fail here */
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pcic_speculative = 1;
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pcic_trapped = 0;
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#endif
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writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
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#if 0 /* does not fail here */
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nop();
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if (pcic_trapped) {
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local_irq_restore(flags);
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*value = ~0;
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return 0;
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}
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#endif
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pcic_speculative = 2;
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pcic_trapped = 0;
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*value = readl(pcic->pcic_config_space_data + (where&4));
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nop();
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if (pcic_trapped) {
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pcic_speculative = 0;
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local_irq_restore(flags);
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*value = ~0;
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return 0;
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}
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pcic_speculative = 0;
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local_irq_restore(flags);
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return 0;
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}
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static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned int v;
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if (bus->number != 0) return -EINVAL;
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switch (size) {
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case 1:
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pcic_read_config_dword(bus->number, devfn, where&~3, &v);
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*val = 0xff & (v >> (8*(where & 3)));
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return 0;
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case 2:
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if (where&1) return -EINVAL;
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pcic_read_config_dword(bus->number, devfn, where&~3, &v);
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*val = 0xffff & (v >> (8*(where & 3)));
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return 0;
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case 4:
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if (where&3) return -EINVAL;
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pcic_read_config_dword(bus->number, devfn, where&~3, val);
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return 0;
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}
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return -EINVAL;
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}
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static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
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int where, u32 value)
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{
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struct linux_pcic *pcic;
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unsigned long flags;
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pcic = &pcic0;
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local_irq_save(flags);
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writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
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writel(value, pcic->pcic_config_space_data + (where&4));
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local_irq_restore(flags);
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return 0;
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}
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static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned int v;
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if (bus->number != 0) return -EINVAL;
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switch (size) {
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case 1:
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pcic_read_config_dword(bus->number, devfn, where&~3, &v);
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|
v = (v & ~(0xff << (8*(where&3)))) |
|
|
|
|
((0xff&val) << (8*(where&3)));
|
|
|
|
return pcic_write_config_dword(bus->number, devfn, where&~3, v);
|
|
|
|
case 2:
|
|
|
|
if (where&1) return -EINVAL;
|
|
|
|
pcic_read_config_dword(bus->number, devfn, where&~3, &v);
|
|
|
|
v = (v & ~(0xffff << (8*(where&3)))) |
|
|
|
|
((0xffff&val) << (8*(where&3)));
|
|
|
|
return pcic_write_config_dword(bus->number, devfn, where&~3, v);
|
|
|
|
case 4:
|
|
|
|
if (where&3) return -EINVAL;
|
|
|
|
return pcic_write_config_dword(bus->number, devfn, where, val);
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_ops pcic_ops = {
|
|
|
|
.read = pcic_read_config,
|
|
|
|
.write = pcic_write_config,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On sparc64 pcibios_init() calls pci_controller_probe().
|
|
|
|
* We want PCIC probed little ahead so that interrupt controller
|
|
|
|
* would be operational.
|
|
|
|
*/
|
|
|
|
int __init pcic_probe(void)
|
|
|
|
{
|
|
|
|
struct linux_pcic *pcic;
|
|
|
|
struct linux_prom_registers regs[PROMREG_MAX];
|
|
|
|
struct linux_pbm_info* pbm;
|
|
|
|
char namebuf[64];
|
2010-10-09 04:18:11 +07:00
|
|
|
phandle node;
|
2005-04-17 05:20:36 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
if (pcic0_up) {
|
|
|
|
prom_printf("PCIC: called twice!\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
pcic = &pcic0;
|
|
|
|
|
|
|
|
node = prom_getchild (prom_root_node);
|
|
|
|
node = prom_searchsiblings (node, "pci");
|
|
|
|
if (node == 0)
|
|
|
|
return -ENODEV;
|
|
|
|
/*
|
|
|
|
* Map in PCIC register set, config space, and IO base
|
|
|
|
*/
|
|
|
|
err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
|
|
|
|
if (err == 0 || err == -1) {
|
|
|
|
prom_printf("PCIC: Error, cannot get PCIC registers "
|
|
|
|
"from PROM.\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
pcic0_up = 1;
|
|
|
|
|
|
|
|
pcic->pcic_res_regs.name = "pcic_registers";
|
|
|
|
pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
|
|
|
|
if (!pcic->pcic_regs) {
|
|
|
|
prom_printf("PCIC: Error, cannot map PCIC registers.\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
pcic->pcic_res_io.name = "pcic_io";
|
|
|
|
if ((pcic->pcic_io = (unsigned long)
|
|
|
|
ioremap(regs[1].phys_addr, 0x10000)) == 0) {
|
|
|
|
prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
|
|
|
|
if ((pcic->pcic_config_space_addr =
|
2014-05-17 04:25:42 +07:00
|
|
|
ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
|
2007-11-20 14:45:16 +07:00
|
|
|
prom_printf("PCIC: Error, cannot map "
|
2005-04-17 05:20:36 +07:00
|
|
|
"PCI Configuration Space Address.\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Docs say three least significant bits in address and data
|
|
|
|
* must be the same. Thus, we need adjust size of data.
|
|
|
|
*/
|
|
|
|
pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
|
|
|
|
if ((pcic->pcic_config_space_data =
|
2014-05-17 04:25:42 +07:00
|
|
|
ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
|
2007-11-20 14:45:16 +07:00
|
|
|
prom_printf("PCIC: Error, cannot map "
|
2005-04-17 05:20:36 +07:00
|
|
|
"PCI Configuration Space Data.\n");
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
|
|
|
|
pbm = &pcic->pbm;
|
|
|
|
pbm->prom_node = node;
|
|
|
|
prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
|
|
|
|
strcpy(pbm->prom_name, namebuf);
|
|
|
|
|
|
|
|
{
|
2011-08-18 05:14:57 +07:00
|
|
|
extern int pcic_nmi_trap_patch[4];
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
t_nmi[0] = pcic_nmi_trap_patch[0];
|
|
|
|
t_nmi[1] = pcic_nmi_trap_patch[1];
|
|
|
|
t_nmi[2] = pcic_nmi_trap_patch[2];
|
|
|
|
t_nmi[3] = pcic_nmi_trap_patch[3];
|
|
|
|
swift_flush_dcache();
|
|
|
|
pcic_regs = pcic->pcic_regs;
|
|
|
|
}
|
|
|
|
|
|
|
|
prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
|
|
|
|
{
|
|
|
|
struct pcic_sn2list *p;
|
|
|
|
|
|
|
|
for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
|
|
|
|
if (strcmp(namebuf, p->sysname) == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
pcic->pcic_imap = p->intmap;
|
|
|
|
pcic->pcic_imdim = p->mapdim;
|
|
|
|
}
|
|
|
|
if (pcic->pcic_imap == NULL) {
|
|
|
|
/*
|
|
|
|
* We do not panic here for the sake of embedded systems.
|
|
|
|
*/
|
|
|
|
printk("PCIC: System %s is unknown, cannot route interrupts\n",
|
|
|
|
namebuf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
|
|
|
|
{
|
|
|
|
struct linux_pbm_info *pbm = &pcic->pbm;
|
|
|
|
|
|
|
|
pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
|
2015-03-09 09:33:58 +07:00
|
|
|
if (!pbm->pci_bus)
|
|
|
|
return;
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#if 0 /* deadwood transplanted from sparc64 */
|
|
|
|
pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
|
|
|
|
pci_record_assignments(pbm, pbm->pci_bus);
|
|
|
|
pci_assign_unassigned(pbm, pbm->pci_bus);
|
|
|
|
pci_fixup_irq(pbm, pbm->pci_bus);
|
|
|
|
#endif
|
2015-03-09 09:33:58 +07:00
|
|
|
pci_bus_add_devices(pbm->pci_bus);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Main entry point from the PCI subsystem.
|
|
|
|
*/
|
|
|
|
static int __init pcic_init(void)
|
|
|
|
{
|
|
|
|
struct linux_pcic *pcic;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCIC should be initialized at start of the timer.
|
|
|
|
* So, here we report the presence of PCIC and do some magic passes.
|
|
|
|
*/
|
|
|
|
if(!pcic0_up)
|
|
|
|
return 0;
|
|
|
|
pcic = &pcic0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Switch off IOTLB translation.
|
|
|
|
*/
|
|
|
|
writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
|
|
|
|
pcic->pcic_regs+PCI_DVMA_CONTROL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Increase mapped size for PCI memory space (DMA access).
|
|
|
|
* Should be done in that order (size first, address second).
|
|
|
|
* Why we couldn't set up 4GB and forget about it? XXX
|
|
|
|
*/
|
|
|
|
writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
|
|
|
|
writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
|
|
pcic->pcic_regs+PCI_BASE_ADDRESS_0);
|
|
|
|
|
|
|
|
pcic_pbm_scan_bus(pcic);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pcic_present(void)
|
|
|
|
{
|
|
|
|
return pcic0_up;
|
|
|
|
}
|
|
|
|
|
2012-12-22 05:03:26 +07:00
|
|
|
static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct linux_prom_pci_registers regs[PROMREG_MAX];
|
|
|
|
int err;
|
2010-10-09 04:18:11 +07:00
|
|
|
phandle node = prom_getchild(pbm->prom_node);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
while(node) {
|
|
|
|
err = prom_getproperty(node, "reg",
|
|
|
|
(char *)®s[0], sizeof(regs));
|
|
|
|
if(err != 0 && err != -1) {
|
|
|
|
unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
|
|
|
|
if(devfn == pdev->devfn)
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
node = prom_getsibling(node);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct pcidev_cookie *pci_devcookie_alloc(void)
|
|
|
|
{
|
|
|
|
return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pcic_map_pci_device(struct linux_pcic *pcic,
|
|
|
|
struct pci_dev *dev, int node)
|
|
|
|
{
|
|
|
|
char namebuf[64];
|
|
|
|
unsigned long address;
|
|
|
|
unsigned long flags;
|
|
|
|
int j;
|
|
|
|
|
|
|
|
if (node == 0 || node == -1) {
|
|
|
|
strcpy(namebuf, "???");
|
|
|
|
} else {
|
|
|
|
prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (j = 0; j < 6; j++) {
|
|
|
|
address = dev->resource[j].start;
|
|
|
|
if (address == 0) break; /* are sequential */
|
|
|
|
flags = dev->resource[j].flags;
|
|
|
|
if ((flags & IORESOURCE_IO) != 0) {
|
|
|
|
if (address < 0x10000) {
|
|
|
|
/*
|
|
|
|
* A device responds to I/O cycles on PCI.
|
|
|
|
* We generate these cycles with memory
|
|
|
|
* access into the fixed map (phys 0x30000000).
|
|
|
|
*
|
|
|
|
* Since a device driver does not want to
|
|
|
|
* do ioremap() before accessing PC-style I/O,
|
|
|
|
* we supply virtual, ready to access address.
|
|
|
|
*
|
2005-10-31 06:01:51 +07:00
|
|
|
* Note that request_region()
|
|
|
|
* works for these devices.
|
2005-04-17 05:20:36 +07:00
|
|
|
*
|
|
|
|
* XXX Neat trick, but it's a *bad* idea
|
|
|
|
* to shit into regions like that.
|
|
|
|
* What if we want to allocate one more
|
|
|
|
* PCI base address...
|
|
|
|
*/
|
|
|
|
dev->resource[j].start =
|
|
|
|
pcic->pcic_io + address;
|
|
|
|
dev->resource[j].end = 1; /* XXX */
|
|
|
|
dev->resource[j].flags =
|
|
|
|
(flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* OOPS... PCI Spec allows this. Sun does
|
|
|
|
* not have any devices getting above 64K
|
|
|
|
* so it must be user with a weird I/O
|
|
|
|
* board in a PCI slot. We must remap it
|
|
|
|
* under 64K but it is not done yet. XXX
|
|
|
|
*/
|
2007-11-20 14:45:16 +07:00
|
|
|
printk("PCIC: Skipping I/O space at 0x%lx, "
|
|
|
|
"this will Oops if a driver attaches "
|
2005-04-17 05:20:36 +07:00
|
|
|
"device '%s' at %02x:%02x)\n", address,
|
|
|
|
namebuf, dev->bus->number, dev->devfn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
|
|
|
|
{
|
|
|
|
struct pcic_ca2irq *p;
|
2011-04-18 18:25:44 +07:00
|
|
|
unsigned int real_irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
int i, ivec;
|
|
|
|
char namebuf[64];
|
|
|
|
|
|
|
|
if (node == 0 || node == -1) {
|
|
|
|
strcpy(namebuf, "???");
|
|
|
|
} else {
|
|
|
|
prom_getstring(node, "name", namebuf, sizeof(namebuf));
|
|
|
|
}
|
|
|
|
|
2014-05-17 04:25:42 +07:00
|
|
|
if ((p = pcic->pcic_imap) == NULL) {
|
2005-04-17 05:20:36 +07:00
|
|
|
dev->irq = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (i = 0; i < pcic->pcic_imdim; i++) {
|
|
|
|
if (p->busno == dev->bus->number && p->devfn == dev->devfn)
|
|
|
|
break;
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
if (i >= pcic->pcic_imdim) {
|
|
|
|
printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
|
|
|
|
namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
|
|
|
|
dev->irq = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
i = p->pin;
|
|
|
|
if (i >= 0 && i < 4) {
|
|
|
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
|
2011-04-18 18:25:44 +07:00
|
|
|
real_irq = ivec >> (i << 2) & 0xF;
|
2005-04-17 05:20:36 +07:00
|
|
|
} else if (i >= 4 && i < 8) {
|
|
|
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
|
2011-04-18 18:25:44 +07:00
|
|
|
real_irq = ivec >> ((i-4) << 2) & 0xF;
|
2005-04-17 05:20:36 +07:00
|
|
|
} else { /* Corrupted map */
|
|
|
|
printk("PCIC: BAD PIN %d\n", i); for (;;) {}
|
|
|
|
}
|
|
|
|
/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
/* real_irq means PROM did not bother to program the upper
|
2005-04-17 05:20:36 +07:00
|
|
|
* half of PCIC. This happens on JS-E with PROM 3.11, for instance.
|
|
|
|
*/
|
2011-04-18 18:25:44 +07:00
|
|
|
if (real_irq == 0 || p->force) {
|
2005-04-17 05:20:36 +07:00
|
|
|
if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
|
|
|
|
printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
|
|
|
|
}
|
|
|
|
printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
|
|
|
|
p->irq, p->pin, dev->bus->number, dev->devfn);
|
2011-04-18 18:25:44 +07:00
|
|
|
real_irq = p->irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
i = p->pin;
|
|
|
|
if (i >= 4) {
|
|
|
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
|
|
|
|
ivec &= ~(0xF << ((i - 4) << 2));
|
|
|
|
ivec |= p->irq << ((i - 4) << 2);
|
|
|
|
writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
|
|
|
|
} else {
|
|
|
|
ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
|
|
|
|
ivec &= ~(0xF << (i << 2));
|
|
|
|
ivec |= p->irq << (i << 2);
|
|
|
|
writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
|
|
|
|
}
|
2011-04-18 18:25:44 +07:00
|
|
|
}
|
|
|
|
dev->irq = pcic_build_device_irq(NULL, real_irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Normally called from {do_}pci_scan_bus...
|
|
|
|
*/
|
2012-12-22 05:03:26 +07:00
|
|
|
void pcibios_fixup_bus(struct pci_bus *bus)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct linux_pcic *pcic;
|
|
|
|
/* struct linux_pbm_info* pbm = &pcic->pbm; */
|
|
|
|
int node;
|
|
|
|
struct pcidev_cookie *pcp;
|
|
|
|
|
|
|
|
if (!pcic0_up) {
|
|
|
|
printk("pcibios_fixup_bus: no PCIC\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
pcic = &pcic0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
|
|
|
|
*/
|
|
|
|
if (bus->number != 0) {
|
|
|
|
printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
|
|
node = pdev_to_pnode(&pcic->pbm, dev);
|
|
|
|
if(node == 0)
|
|
|
|
node = -1;
|
|
|
|
|
|
|
|
/* cookies */
|
|
|
|
pcp = pci_devcookie_alloc();
|
|
|
|
pcp->pbm = &pcic->pbm;
|
2006-06-24 05:53:31 +07:00
|
|
|
pcp->prom_node = of_find_node_by_phandle(node);
|
2005-04-17 05:20:36 +07:00
|
|
|
dev->sysdata = pcp;
|
|
|
|
|
|
|
|
/* fixing I/O to look like memory */
|
|
|
|
if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
|
|
|
|
pcic_map_pci_device(pcic, dev, node);
|
|
|
|
|
|
|
|
pcic_fill_irq(pcic, dev, node);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-22 06:35:49 +07:00
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|
|
|
{
|
|
|
|
u16 cmd, oldcmd;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
oldcmd = cmd;
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
|
|
struct resource *res = &dev->resource[i];
|
|
|
|
|
|
|
|
/* Only set up the requested stuff */
|
|
|
|
if (!(mask & (1<<i)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
|
|
|
cmd |= PCI_COMMAND_IO;
|
|
|
|
if (res->flags & IORESOURCE_MEM)
|
|
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd != oldcmd) {
|
|
|
|
printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
|
|
|
|
pci_name(dev), cmd);
|
|
|
|
/* Enable the appropriate bits in the PCI command register. */
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Makes compiler happy */
|
|
|
|
static volatile int pcic_timer_dummy;
|
|
|
|
|
|
|
|
static void pcic_clear_clock_irq(void)
|
|
|
|
{
|
|
|
|
pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
|
|
|
|
}
|
|
|
|
|
2012-04-05 02:49:26 +07:00
|
|
|
/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
|
|
|
|
#define USECS_PER_JIFFY (1000000 / HZ)
|
|
|
|
#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
|
|
|
|
|
|
|
|
static unsigned int pcic_cycles_offset(void)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2012-04-05 02:49:26 +07:00
|
|
|
u32 value, count;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-04-05 02:49:26 +07:00
|
|
|
value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
|
|
|
|
count = value & ~PCI_SYS_COUNTER_OVERFLOW;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-04-05 02:49:26 +07:00
|
|
|
if (value & PCI_SYS_COUNTER_OVERFLOW)
|
|
|
|
count += TICK_TIMER_LIMIT;
|
2010-01-15 16:34:28 +07:00
|
|
|
/*
|
2012-04-05 02:49:26 +07:00
|
|
|
* We divide all by HZ
|
2010-01-15 16:34:28 +07:00
|
|
|
* to have microsecond resolution and to avoid overflow
|
|
|
|
*/
|
2012-04-05 02:49:26 +07:00
|
|
|
count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
|
2010-01-15 16:34:28 +07:00
|
|
|
|
2012-04-17 02:50:49 +07:00
|
|
|
/* Coordinate with the sparc_config.clock_rate setting */
|
2012-04-05 02:49:26 +07:00
|
|
|
return count * 2;
|
|
|
|
}
|
2010-01-15 16:34:28 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
void __init pci_time_init(void)
|
|
|
|
{
|
|
|
|
struct linux_pcic *pcic = &pcic0;
|
|
|
|
unsigned long v;
|
|
|
|
int timer_irq, irq;
|
2011-04-18 18:25:44 +07:00
|
|
|
int err;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-04-05 02:49:26 +07:00
|
|
|
#ifndef CONFIG_SMP
|
|
|
|
/*
|
2012-04-17 02:50:49 +07:00
|
|
|
* The clock_rate is in SBUS dimension.
|
2012-04-05 02:49:26 +07:00
|
|
|
* We take into account this in pcic_cycles_offset()
|
|
|
|
*/
|
2012-04-17 02:50:49 +07:00
|
|
|
sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
|
2012-04-05 02:49:26 +07:00
|
|
|
sparc_config.features |= FEAT_L10_CLOCKEVENT;
|
|
|
|
#endif
|
|
|
|
sparc_config.features |= FEAT_L10_CLOCKSOURCE;
|
|
|
|
sparc_config.get_cycles_offset = pcic_cycles_offset;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
|
|
|
|
/* PROM should set appropriate irq */
|
|
|
|
v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
|
|
|
|
timer_irq = PCI_COUNTER_IRQ_SYS(v);
|
|
|
|
writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
|
|
|
|
pcic->pcic_regs+PCI_COUNTER_IRQ);
|
2011-04-18 18:25:44 +07:00
|
|
|
irq = pcic_build_device_irq(NULL, timer_irq);
|
2012-04-05 02:49:26 +07:00
|
|
|
err = request_irq(irq, timer_interrupt,
|
2011-04-18 18:25:44 +07:00
|
|
|
IRQF_TIMER, "timer", NULL);
|
|
|
|
if (err) {
|
2005-04-17 05:20:36 +07:00
|
|
|
prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
local_irq_enable();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
static void watchdog_reset() {
|
|
|
|
writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* NMI
|
|
|
|
*/
|
|
|
|
void pcic_nmi(unsigned int pend, struct pt_regs *regs)
|
|
|
|
{
|
2014-04-26 14:57:35 +07:00
|
|
|
pend = swab32(pend);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
|
|
|
|
/*
|
|
|
|
* XXX On CP-1200 PCI #SERR may happen, we do not know
|
|
|
|
* what to do about it yet.
|
|
|
|
*/
|
|
|
|
printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
|
|
|
|
pend, (int)regs->pc, pcic_speculative);
|
|
|
|
for (;;) { }
|
|
|
|
}
|
|
|
|
pcic_speculative = 0;
|
|
|
|
pcic_trapped = 1;
|
|
|
|
regs->pc = regs->npc;
|
|
|
|
regs->npc += 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long get_irqmask(int irq_nr)
|
|
|
|
{
|
|
|
|
return 1 << irq_nr;
|
|
|
|
}
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
static void pcic_mask_irq(struct irq_data *data)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
unsigned long mask, flags;
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
mask = (unsigned long)data->chip_data;
|
2005-04-17 05:20:36 +07:00
|
|
|
local_irq_save(flags);
|
|
|
|
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
static void pcic_unmask_irq(struct irq_data *data)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
unsigned long mask, flags;
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
mask = (unsigned long)data->chip_data;
|
2005-04-17 05:20:36 +07:00
|
|
|
local_irq_save(flags);
|
|
|
|
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
static unsigned int pcic_startup_irq(struct irq_data *data)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2011-04-18 18:25:44 +07:00
|
|
|
irq_link(data->irq);
|
|
|
|
pcic_unmask_irq(data);
|
|
|
|
return 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
static struct irq_chip pcic_irq = {
|
|
|
|
.name = "pcic",
|
|
|
|
.irq_startup = pcic_startup_irq,
|
|
|
|
.irq_mask = pcic_mask_irq,
|
|
|
|
.irq_unmask = pcic_unmask_irq,
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned int pcic_build_device_irq(struct platform_device *op,
|
|
|
|
unsigned int real_irq)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2011-04-18 18:25:44 +07:00
|
|
|
unsigned int irq;
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
irq = 0;
|
|
|
|
mask = get_irqmask(real_irq);
|
|
|
|
if (mask == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
irq = irq_alloc(real_irq, real_irq);
|
|
|
|
if (irq == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
irq_set_chip_and_handler_name(irq, &pcic_irq,
|
|
|
|
handle_level_irq, "PCIC");
|
|
|
|
irq_set_chip_data(irq, (void *)mask);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2011-04-18 18:25:44 +07:00
|
|
|
|
|
|
|
static void pcic_load_profile_irq(int cpu, unsigned int limit)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2011-04-18 18:25:44 +07:00
|
|
|
printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init sun4m_pci_init_IRQ(void)
|
|
|
|
{
|
2012-04-04 18:21:13 +07:00
|
|
|
sparc_config.build_device_irq = pcic_build_device_irq;
|
2012-05-14 22:30:35 +07:00
|
|
|
sparc_config.clear_clock_irq = pcic_clear_clock_irq;
|
|
|
|
sparc_config.load_profile_irq = pcic_load_profile_irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
subsys_initcall(pcic_init);
|