mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:26:42 +07:00
966 lines
25 KiB
C
966 lines
25 KiB
C
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/*
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* Texas Instruments CPDMA Driver
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include "davinci_cpdma.h"
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/* DMA Registers */
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#define CPDMA_TXIDVER 0x00
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#define CPDMA_TXCONTROL 0x04
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#define CPDMA_TXTEARDOWN 0x08
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#define CPDMA_RXIDVER 0x10
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#define CPDMA_RXCONTROL 0x14
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#define CPDMA_SOFTRESET 0x1c
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#define CPDMA_RXTEARDOWN 0x18
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#define CPDMA_TXINTSTATRAW 0x80
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#define CPDMA_TXINTSTATMASKED 0x84
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#define CPDMA_TXINTMASKSET 0x88
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#define CPDMA_TXINTMASKCLEAR 0x8c
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#define CPDMA_MACINVECTOR 0x90
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#define CPDMA_MACEOIVECTOR 0x94
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#define CPDMA_RXINTSTATRAW 0xa0
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#define CPDMA_RXINTSTATMASKED 0xa4
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#define CPDMA_RXINTMASKSET 0xa8
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#define CPDMA_RXINTMASKCLEAR 0xac
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#define CPDMA_DMAINTSTATRAW 0xb0
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#define CPDMA_DMAINTSTATMASKED 0xb4
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#define CPDMA_DMAINTMASKSET 0xb8
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#define CPDMA_DMAINTMASKCLEAR 0xbc
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#define CPDMA_DMAINT_HOSTERR BIT(1)
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/* the following exist only if has_ext_regs is set */
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#define CPDMA_DMACONTROL 0x20
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#define CPDMA_DMASTATUS 0x24
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#define CPDMA_RXBUFFOFS 0x28
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#define CPDMA_EM_CONTROL 0x2c
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/* Descriptor mode bits */
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#define CPDMA_DESC_SOP BIT(31)
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#define CPDMA_DESC_EOP BIT(30)
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#define CPDMA_DESC_OWNER BIT(29)
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#define CPDMA_DESC_EOQ BIT(28)
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#define CPDMA_DESC_TD_COMPLETE BIT(27)
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#define CPDMA_DESC_PASS_CRC BIT(26)
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#define CPDMA_TEARDOWN_VALUE 0xfffffffc
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struct cpdma_desc {
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/* hardware fields */
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u32 hw_next;
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u32 hw_buffer;
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u32 hw_len;
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u32 hw_mode;
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/* software fields */
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void *sw_token;
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u32 sw_buffer;
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u32 sw_len;
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};
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struct cpdma_desc_pool {
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u32 phys;
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void __iomem *iomap; /* ioremap map */
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void *cpumap; /* dma_alloc map */
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int desc_size, mem_size;
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int num_desc, used_desc;
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unsigned long *bitmap;
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struct device *dev;
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spinlock_t lock;
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};
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enum cpdma_state {
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CPDMA_STATE_IDLE,
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CPDMA_STATE_ACTIVE,
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CPDMA_STATE_TEARDOWN,
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};
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const char *cpdma_state_str[] = { "idle", "active", "teardown" };
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struct cpdma_ctlr {
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enum cpdma_state state;
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struct cpdma_params params;
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struct device *dev;
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struct cpdma_desc_pool *pool;
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spinlock_t lock;
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struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS];
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};
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struct cpdma_chan {
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enum cpdma_state state;
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struct cpdma_ctlr *ctlr;
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int chan_num;
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spinlock_t lock;
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struct cpdma_desc __iomem *head, *tail;
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int count;
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void __iomem *hdp, *cp, *rxfree;
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u32 mask;
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cpdma_handler_fn handler;
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enum dma_data_direction dir;
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struct cpdma_chan_stats stats;
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/* offsets into dmaregs */
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int int_set, int_clear, td;
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};
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/* The following make access to common cpdma_ctlr params more readable */
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#define dmaregs params.dmaregs
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#define num_chan params.num_chan
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/* various accessors */
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#define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs))
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#define chan_read(chan, fld) __raw_readl((chan)->fld)
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#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
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#define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs))
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#define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld)
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#define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld)
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/*
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* Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci
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* emac) have dedicated on-chip memory for these descriptors. Some other
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* devices (e.g. cpsw switches) use plain old memory. Descriptor pools
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* abstract out these details
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*/
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static struct cpdma_desc_pool *
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cpdma_desc_pool_create(struct device *dev, u32 phys, int size, int align)
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{
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int bitmap_size;
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struct cpdma_desc_pool *pool;
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pool = kzalloc(sizeof(*pool), GFP_KERNEL);
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if (!pool)
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return NULL;
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spin_lock_init(&pool->lock);
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pool->dev = dev;
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pool->mem_size = size;
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pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align);
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pool->num_desc = size / pool->desc_size;
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bitmap_size = (pool->num_desc / BITS_PER_LONG) * sizeof(long);
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pool->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
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if (!pool->bitmap)
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goto fail;
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if (phys) {
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pool->phys = phys;
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pool->iomap = ioremap(phys, size);
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} else {
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pool->cpumap = dma_alloc_coherent(dev, size, &pool->phys,
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GFP_KERNEL);
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pool->iomap = (void __force __iomem *)pool->cpumap;
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}
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if (pool->iomap)
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return pool;
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fail:
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kfree(pool->bitmap);
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kfree(pool);
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return NULL;
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}
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static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
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{
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unsigned long flags;
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if (!pool)
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return;
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spin_lock_irqsave(&pool->lock, flags);
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WARN_ON(pool->used_desc);
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kfree(pool->bitmap);
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if (pool->cpumap) {
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dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
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pool->phys);
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} else {
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iounmap(pool->iomap);
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}
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spin_unlock_irqrestore(&pool->lock, flags);
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kfree(pool);
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}
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static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
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struct cpdma_desc __iomem *desc)
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{
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if (!desc)
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return 0;
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return pool->phys + (__force dma_addr_t)desc -
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(__force dma_addr_t)pool->iomap;
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}
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static inline struct cpdma_desc __iomem *
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desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
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{
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return dma ? pool->iomap + dma - pool->phys : NULL;
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}
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static struct cpdma_desc __iomem *
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cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc)
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{
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unsigned long flags;
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int index;
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struct cpdma_desc __iomem *desc = NULL;
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spin_lock_irqsave(&pool->lock, flags);
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index = bitmap_find_next_zero_area(pool->bitmap, pool->num_desc, 0,
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num_desc, 0);
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if (index < pool->num_desc) {
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bitmap_set(pool->bitmap, index, num_desc);
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desc = pool->iomap + pool->desc_size * index;
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pool->used_desc++;
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}
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spin_unlock_irqrestore(&pool->lock, flags);
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return desc;
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}
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static void cpdma_desc_free(struct cpdma_desc_pool *pool,
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struct cpdma_desc __iomem *desc, int num_desc)
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{
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unsigned long flags, index;
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index = ((unsigned long)desc - (unsigned long)pool->iomap) /
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pool->desc_size;
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spin_lock_irqsave(&pool->lock, flags);
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bitmap_clear(pool->bitmap, index, num_desc);
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pool->used_desc--;
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spin_unlock_irqrestore(&pool->lock, flags);
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}
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
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{
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struct cpdma_ctlr *ctlr;
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ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
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if (!ctlr)
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return NULL;
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ctlr->state = CPDMA_STATE_IDLE;
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ctlr->params = *params;
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ctlr->dev = params->dev;
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spin_lock_init(&ctlr->lock);
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ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
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ctlr->params.desc_mem_phys,
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ctlr->params.desc_mem_size,
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ctlr->params.desc_align);
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if (!ctlr->pool) {
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kfree(ctlr);
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return NULL;
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}
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if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
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ctlr->num_chan = CPDMA_MAX_CHANNELS;
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return ctlr;
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}
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&ctlr->lock, flags);
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if (ctlr->state != CPDMA_STATE_IDLE) {
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return -EBUSY;
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}
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if (ctlr->params.has_soft_reset) {
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unsigned long timeout = jiffies + HZ/10;
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dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
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while (time_before(jiffies, timeout)) {
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if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
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break;
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}
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WARN_ON(!time_before(jiffies, timeout));
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}
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for (i = 0; i < ctlr->num_chan; i++) {
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__raw_writel(0, ctlr->params.txhdp + 4 * i);
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__raw_writel(0, ctlr->params.rxhdp + 4 * i);
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__raw_writel(0, ctlr->params.txcp + 4 * i);
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__raw_writel(0, ctlr->params.rxcp + 4 * i);
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}
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dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
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dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
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dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
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dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
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ctlr->state = CPDMA_STATE_ACTIVE;
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for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
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if (ctlr->channels[i])
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cpdma_chan_start(ctlr->channels[i]);
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}
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return 0;
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}
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int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
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{
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unsigned long flags;
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int i;
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spin_lock_irqsave(&ctlr->lock, flags);
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if (ctlr->state != CPDMA_STATE_ACTIVE) {
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return -EINVAL;
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}
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ctlr->state = CPDMA_STATE_TEARDOWN;
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for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
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if (ctlr->channels[i])
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cpdma_chan_stop(ctlr->channels[i]);
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}
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|
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dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
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dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
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|
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dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
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dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
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|
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ctlr->state = CPDMA_STATE_IDLE;
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|
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spin_unlock_irqrestore(&ctlr->lock, flags);
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return 0;
|
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}
|
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|
|
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int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
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{
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struct device *dev = ctlr->dev;
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unsigned long flags;
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int i;
|
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|
|
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spin_lock_irqsave(&ctlr->lock, flags);
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|
|
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dev_info(dev, "CPDMA: state: %s", cpdma_state_str[ctlr->state]);
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|
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dev_info(dev, "CPDMA: txidver: %x",
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dma_reg_read(ctlr, CPDMA_TXIDVER));
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dev_info(dev, "CPDMA: txcontrol: %x",
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dma_reg_read(ctlr, CPDMA_TXCONTROL));
|
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dev_info(dev, "CPDMA: txteardown: %x",
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dma_reg_read(ctlr, CPDMA_TXTEARDOWN));
|
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dev_info(dev, "CPDMA: rxidver: %x",
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dma_reg_read(ctlr, CPDMA_RXIDVER));
|
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dev_info(dev, "CPDMA: rxcontrol: %x",
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dma_reg_read(ctlr, CPDMA_RXCONTROL));
|
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dev_info(dev, "CPDMA: softreset: %x",
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dma_reg_read(ctlr, CPDMA_SOFTRESET));
|
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dev_info(dev, "CPDMA: rxteardown: %x",
|
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dma_reg_read(ctlr, CPDMA_RXTEARDOWN));
|
||
|
dev_info(dev, "CPDMA: txintstatraw: %x",
|
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dma_reg_read(ctlr, CPDMA_TXINTSTATRAW));
|
||
|
dev_info(dev, "CPDMA: txintstatmasked: %x",
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|
dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED));
|
||
|
dev_info(dev, "CPDMA: txintmaskset: %x",
|
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|
dma_reg_read(ctlr, CPDMA_TXINTMASKSET));
|
||
|
dev_info(dev, "CPDMA: txintmaskclear: %x",
|
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|
dma_reg_read(ctlr, CPDMA_TXINTMASKCLEAR));
|
||
|
dev_info(dev, "CPDMA: macinvector: %x",
|
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|
dma_reg_read(ctlr, CPDMA_MACINVECTOR));
|
||
|
dev_info(dev, "CPDMA: maceoivector: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_MACEOIVECTOR));
|
||
|
dev_info(dev, "CPDMA: rxintstatraw: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_RXINTSTATRAW));
|
||
|
dev_info(dev, "CPDMA: rxintstatmasked: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED));
|
||
|
dev_info(dev, "CPDMA: rxintmaskset: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_RXINTMASKSET));
|
||
|
dev_info(dev, "CPDMA: rxintmaskclear: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_RXINTMASKCLEAR));
|
||
|
dev_info(dev, "CPDMA: dmaintstatraw: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMAINTSTATRAW));
|
||
|
dev_info(dev, "CPDMA: dmaintstatmasked: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMAINTSTATMASKED));
|
||
|
dev_info(dev, "CPDMA: dmaintmaskset: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMAINTMASKSET));
|
||
|
dev_info(dev, "CPDMA: dmaintmaskclear: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMAINTMASKCLEAR));
|
||
|
|
||
|
if (!ctlr->params.has_ext_regs) {
|
||
|
dev_info(dev, "CPDMA: dmacontrol: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMACONTROL));
|
||
|
dev_info(dev, "CPDMA: dmastatus: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_DMASTATUS));
|
||
|
dev_info(dev, "CPDMA: rxbuffofs: %x",
|
||
|
dma_reg_read(ctlr, CPDMA_RXBUFFOFS));
|
||
|
}
|
||
|
|
||
|
for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
|
||
|
if (ctlr->channels[i])
|
||
|
cpdma_chan_dump(ctlr->channels[i]);
|
||
|
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
int ret = 0, i;
|
||
|
|
||
|
if (!ctlr)
|
||
|
return -EINVAL;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
if (ctlr->state != CPDMA_STATE_IDLE)
|
||
|
cpdma_ctlr_stop(ctlr);
|
||
|
|
||
|
for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
|
||
|
if (ctlr->channels[i])
|
||
|
cpdma_chan_destroy(ctlr->channels[i]);
|
||
|
}
|
||
|
|
||
|
cpdma_desc_pool_destroy(ctlr->pool);
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
kfree(ctlr);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
int i, reg;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
if (ctlr->state != CPDMA_STATE_ACTIVE) {
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR;
|
||
|
dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);
|
||
|
|
||
|
for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
|
||
|
if (ctlr->channels[i])
|
||
|
cpdma_chan_int_ctrl(ctlr->channels[i], enable);
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr)
|
||
|
{
|
||
|
dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0);
|
||
|
}
|
||
|
|
||
|
struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
|
||
|
cpdma_handler_fn handler)
|
||
|
{
|
||
|
struct cpdma_chan *chan;
|
||
|
int ret, offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
|
||
|
unsigned long flags;
|
||
|
|
||
|
if (__chan_linear(chan_num) >= ctlr->num_chan)
|
||
|
return NULL;
|
||
|
|
||
|
ret = -ENOMEM;
|
||
|
chan = kzalloc(sizeof(*chan), GFP_KERNEL);
|
||
|
if (!chan)
|
||
|
goto err_chan_alloc;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
ret = -EBUSY;
|
||
|
if (ctlr->channels[chan_num])
|
||
|
goto err_chan_busy;
|
||
|
|
||
|
chan->ctlr = ctlr;
|
||
|
chan->state = CPDMA_STATE_IDLE;
|
||
|
chan->chan_num = chan_num;
|
||
|
chan->handler = handler;
|
||
|
|
||
|
if (is_rx_chan(chan)) {
|
||
|
chan->hdp = ctlr->params.rxhdp + offset;
|
||
|
chan->cp = ctlr->params.rxcp + offset;
|
||
|
chan->rxfree = ctlr->params.rxfree + offset;
|
||
|
chan->int_set = CPDMA_RXINTMASKSET;
|
||
|
chan->int_clear = CPDMA_RXINTMASKCLEAR;
|
||
|
chan->td = CPDMA_RXTEARDOWN;
|
||
|
chan->dir = DMA_FROM_DEVICE;
|
||
|
} else {
|
||
|
chan->hdp = ctlr->params.txhdp + offset;
|
||
|
chan->cp = ctlr->params.txcp + offset;
|
||
|
chan->int_set = CPDMA_TXINTMASKSET;
|
||
|
chan->int_clear = CPDMA_TXINTMASKCLEAR;
|
||
|
chan->td = CPDMA_TXTEARDOWN;
|
||
|
chan->dir = DMA_TO_DEVICE;
|
||
|
}
|
||
|
chan->mask = BIT(chan_linear(chan));
|
||
|
|
||
|
spin_lock_init(&chan->lock);
|
||
|
|
||
|
ctlr->channels[chan_num] = chan;
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return chan;
|
||
|
|
||
|
err_chan_busy:
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
kfree(chan);
|
||
|
err_chan_alloc:
|
||
|
return ERR_PTR(ret);
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_destroy(struct cpdma_chan *chan)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
unsigned long flags;
|
||
|
|
||
|
if (!chan)
|
||
|
return -EINVAL;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
if (chan->state != CPDMA_STATE_IDLE)
|
||
|
cpdma_chan_stop(chan);
|
||
|
ctlr->channels[chan->chan_num] = NULL;
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
kfree(chan);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_get_stats(struct cpdma_chan *chan,
|
||
|
struct cpdma_chan_stats *stats)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
if (!chan)
|
||
|
return -EINVAL;
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
memcpy(stats, &chan->stats, sizeof(*stats));
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_dump(struct cpdma_chan *chan)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
struct device *dev = chan->ctlr->dev;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
|
||
|
dev_info(dev, "channel %d (%s %d) state %s",
|
||
|
chan->chan_num, is_rx_chan(chan) ? "rx" : "tx",
|
||
|
chan_linear(chan), cpdma_state_str[chan->state]);
|
||
|
dev_info(dev, "\thdp: %x\n", chan_read(chan, hdp));
|
||
|
dev_info(dev, "\tcp: %x\n", chan_read(chan, cp));
|
||
|
if (chan->rxfree) {
|
||
|
dev_info(dev, "\trxfree: %x\n",
|
||
|
chan_read(chan, rxfree));
|
||
|
}
|
||
|
|
||
|
dev_info(dev, "\tstats head_enqueue: %d\n",
|
||
|
chan->stats.head_enqueue);
|
||
|
dev_info(dev, "\tstats tail_enqueue: %d\n",
|
||
|
chan->stats.tail_enqueue);
|
||
|
dev_info(dev, "\tstats pad_enqueue: %d\n",
|
||
|
chan->stats.pad_enqueue);
|
||
|
dev_info(dev, "\tstats misqueued: %d\n",
|
||
|
chan->stats.misqueued);
|
||
|
dev_info(dev, "\tstats desc_alloc_fail: %d\n",
|
||
|
chan->stats.desc_alloc_fail);
|
||
|
dev_info(dev, "\tstats pad_alloc_fail: %d\n",
|
||
|
chan->stats.pad_alloc_fail);
|
||
|
dev_info(dev, "\tstats runt_receive_buff: %d\n",
|
||
|
chan->stats.runt_receive_buff);
|
||
|
dev_info(dev, "\tstats runt_transmit_buff: %d\n",
|
||
|
chan->stats.runt_transmit_buff);
|
||
|
dev_info(dev, "\tstats empty_dequeue: %d\n",
|
||
|
chan->stats.empty_dequeue);
|
||
|
dev_info(dev, "\tstats busy_dequeue: %d\n",
|
||
|
chan->stats.busy_dequeue);
|
||
|
dev_info(dev, "\tstats good_dequeue: %d\n",
|
||
|
chan->stats.good_dequeue);
|
||
|
dev_info(dev, "\tstats requeue: %d\n",
|
||
|
chan->stats.requeue);
|
||
|
dev_info(dev, "\tstats teardown_dequeue: %d\n",
|
||
|
chan->stats.teardown_dequeue);
|
||
|
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void __cpdma_chan_submit(struct cpdma_chan *chan,
|
||
|
struct cpdma_desc __iomem *desc)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc __iomem *prev = chan->tail;
|
||
|
struct cpdma_desc_pool *pool = ctlr->pool;
|
||
|
dma_addr_t desc_dma;
|
||
|
u32 mode;
|
||
|
|
||
|
desc_dma = desc_phys(pool, desc);
|
||
|
|
||
|
/* simple case - idle channel */
|
||
|
if (!chan->head) {
|
||
|
chan->stats.head_enqueue++;
|
||
|
chan->head = desc;
|
||
|
chan->tail = desc;
|
||
|
if (chan->state == CPDMA_STATE_ACTIVE)
|
||
|
chan_write(chan, hdp, desc_dma);
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
/* first chain the descriptor at the tail of the list */
|
||
|
desc_write(prev, hw_next, desc_dma);
|
||
|
chan->tail = desc;
|
||
|
chan->stats.tail_enqueue++;
|
||
|
|
||
|
/* next check if EOQ has been triggered already */
|
||
|
mode = desc_read(prev, hw_mode);
|
||
|
if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) &&
|
||
|
(chan->state == CPDMA_STATE_ACTIVE)) {
|
||
|
desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ);
|
||
|
chan_write(chan, hdp, desc_dma);
|
||
|
chan->stats.misqueued++;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
|
||
|
int len, gfp_t gfp_mask)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc __iomem *desc;
|
||
|
dma_addr_t buffer;
|
||
|
unsigned long flags;
|
||
|
u32 mode;
|
||
|
int ret = 0;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
|
||
|
if (chan->state == CPDMA_STATE_TEARDOWN) {
|
||
|
ret = -EINVAL;
|
||
|
goto unlock_ret;
|
||
|
}
|
||
|
|
||
|
desc = cpdma_desc_alloc(ctlr->pool, 1);
|
||
|
if (!desc) {
|
||
|
chan->stats.desc_alloc_fail++;
|
||
|
ret = -ENOMEM;
|
||
|
goto unlock_ret;
|
||
|
}
|
||
|
|
||
|
if (len < ctlr->params.min_packet_size) {
|
||
|
len = ctlr->params.min_packet_size;
|
||
|
chan->stats.runt_transmit_buff++;
|
||
|
}
|
||
|
|
||
|
buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
|
||
|
mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
|
||
|
|
||
|
desc_write(desc, hw_next, 0);
|
||
|
desc_write(desc, hw_buffer, buffer);
|
||
|
desc_write(desc, hw_len, len);
|
||
|
desc_write(desc, hw_mode, mode | len);
|
||
|
desc_write(desc, sw_token, token);
|
||
|
desc_write(desc, sw_buffer, buffer);
|
||
|
desc_write(desc, sw_len, len);
|
||
|
|
||
|
__cpdma_chan_submit(chan, desc);
|
||
|
|
||
|
if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
|
||
|
chan_write(chan, rxfree, 1);
|
||
|
|
||
|
chan->count++;
|
||
|
|
||
|
unlock_ret:
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static void __cpdma_chan_free(struct cpdma_chan *chan,
|
||
|
struct cpdma_desc __iomem *desc,
|
||
|
int outlen, int status)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc_pool *pool = ctlr->pool;
|
||
|
dma_addr_t buff_dma;
|
||
|
int origlen;
|
||
|
void *token;
|
||
|
|
||
|
token = (void *)desc_read(desc, sw_token);
|
||
|
buff_dma = desc_read(desc, sw_buffer);
|
||
|
origlen = desc_read(desc, sw_len);
|
||
|
|
||
|
dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
|
||
|
cpdma_desc_free(pool, desc, 1);
|
||
|
(*chan->handler)(token, outlen, status);
|
||
|
}
|
||
|
|
||
|
static int __cpdma_chan_process(struct cpdma_chan *chan)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc __iomem *desc;
|
||
|
int status, outlen;
|
||
|
struct cpdma_desc_pool *pool = ctlr->pool;
|
||
|
dma_addr_t desc_dma;
|
||
|
unsigned long flags;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
|
||
|
desc = chan->head;
|
||
|
if (!desc) {
|
||
|
chan->stats.empty_dequeue++;
|
||
|
status = -ENOENT;
|
||
|
goto unlock_ret;
|
||
|
}
|
||
|
desc_dma = desc_phys(pool, desc);
|
||
|
|
||
|
status = __raw_readl(&desc->hw_mode);
|
||
|
outlen = status & 0x7ff;
|
||
|
if (status & CPDMA_DESC_OWNER) {
|
||
|
chan->stats.busy_dequeue++;
|
||
|
status = -EBUSY;
|
||
|
goto unlock_ret;
|
||
|
}
|
||
|
status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE);
|
||
|
|
||
|
chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
|
||
|
chan_write(chan, cp, desc_dma);
|
||
|
chan->count--;
|
||
|
chan->stats.good_dequeue++;
|
||
|
|
||
|
if (status & CPDMA_DESC_EOQ) {
|
||
|
chan->stats.requeue++;
|
||
|
chan_write(chan, hdp, desc_phys(pool, chan->head));
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
|
||
|
__cpdma_chan_free(chan, desc, outlen, status);
|
||
|
return status;
|
||
|
|
||
|
unlock_ret:
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return status;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_process(struct cpdma_chan *chan, int quota)
|
||
|
{
|
||
|
int used = 0, ret = 0;
|
||
|
|
||
|
if (chan->state != CPDMA_STATE_ACTIVE)
|
||
|
return -EINVAL;
|
||
|
|
||
|
while (used < quota) {
|
||
|
ret = __cpdma_chan_process(chan);
|
||
|
if (ret < 0)
|
||
|
break;
|
||
|
used++;
|
||
|
}
|
||
|
return used;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_start(struct cpdma_chan *chan)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc_pool *pool = ctlr->pool;
|
||
|
unsigned long flags;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
if (chan->state != CPDMA_STATE_IDLE) {
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return -EBUSY;
|
||
|
}
|
||
|
if (ctlr->state != CPDMA_STATE_ACTIVE) {
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
dma_reg_write(ctlr, chan->int_set, chan->mask);
|
||
|
chan->state = CPDMA_STATE_ACTIVE;
|
||
|
if (chan->head) {
|
||
|
chan_write(chan, hdp, desc_phys(pool, chan->head));
|
||
|
if (chan->rxfree)
|
||
|
chan_write(chan, rxfree, chan->count);
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_stop(struct cpdma_chan *chan)
|
||
|
{
|
||
|
struct cpdma_ctlr *ctlr = chan->ctlr;
|
||
|
struct cpdma_desc_pool *pool = ctlr->pool;
|
||
|
unsigned long flags;
|
||
|
int ret;
|
||
|
unsigned long timeout;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
if (chan->state != CPDMA_STATE_ACTIVE) {
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
chan->state = CPDMA_STATE_TEARDOWN;
|
||
|
dma_reg_write(ctlr, chan->int_clear, chan->mask);
|
||
|
|
||
|
/* trigger teardown */
|
||
|
dma_reg_write(ctlr, chan->td, chan->chan_num);
|
||
|
|
||
|
/* wait for teardown complete */
|
||
|
timeout = jiffies + HZ/10; /* 100 msec */
|
||
|
while (time_before(jiffies, timeout)) {
|
||
|
u32 cp = chan_read(chan, cp);
|
||
|
if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
|
||
|
break;
|
||
|
cpu_relax();
|
||
|
}
|
||
|
WARN_ON(!time_before(jiffies, timeout));
|
||
|
chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
|
||
|
|
||
|
/* handle completed packets */
|
||
|
do {
|
||
|
ret = __cpdma_chan_process(chan);
|
||
|
if (ret < 0)
|
||
|
break;
|
||
|
} while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
|
||
|
|
||
|
/* remaining packets haven't been tx/rx'ed, clean them up */
|
||
|
while (chan->head) {
|
||
|
struct cpdma_desc __iomem *desc = chan->head;
|
||
|
dma_addr_t next_dma;
|
||
|
|
||
|
next_dma = desc_read(desc, hw_next);
|
||
|
chan->head = desc_from_phys(pool, next_dma);
|
||
|
chan->stats.teardown_dequeue++;
|
||
|
|
||
|
/* issue callback without locks held */
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
__cpdma_chan_free(chan, desc, 0, -ENOSYS);
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
}
|
||
|
|
||
|
chan->state = CPDMA_STATE_IDLE;
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
|
||
|
spin_lock_irqsave(&chan->lock, flags);
|
||
|
if (chan->state != CPDMA_STATE_ACTIVE) {
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,
|
||
|
chan->mask);
|
||
|
spin_unlock_irqrestore(&chan->lock, flags);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
struct cpdma_control_info {
|
||
|
u32 reg;
|
||
|
u32 shift, mask;
|
||
|
int access;
|
||
|
#define ACCESS_RO BIT(0)
|
||
|
#define ACCESS_WO BIT(1)
|
||
|
#define ACCESS_RW (ACCESS_RO | ACCESS_WO)
|
||
|
};
|
||
|
|
||
|
struct cpdma_control_info controls[] = {
|
||
|
[CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO},
|
||
|
[CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW},
|
||
|
[CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW},
|
||
|
[CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW},
|
||
|
[CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW},
|
||
|
[CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO},
|
||
|
[CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW},
|
||
|
[CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW},
|
||
|
[CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW},
|
||
|
[CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW},
|
||
|
[CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW},
|
||
|
};
|
||
|
|
||
|
int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
struct cpdma_control_info *info = &controls[control];
|
||
|
int ret;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
|
||
|
ret = -ENOTSUPP;
|
||
|
if (!ctlr->params.has_ext_regs)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -EINVAL;
|
||
|
if (ctlr->state != CPDMA_STATE_ACTIVE)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -ENOENT;
|
||
|
if (control < 0 || control >= ARRAY_SIZE(controls))
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -EPERM;
|
||
|
if ((info->access & ACCESS_RO) != ACCESS_RO)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
|
||
|
|
||
|
unlock_ret:
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
|
||
|
{
|
||
|
unsigned long flags;
|
||
|
struct cpdma_control_info *info = &controls[control];
|
||
|
int ret;
|
||
|
u32 val;
|
||
|
|
||
|
spin_lock_irqsave(&ctlr->lock, flags);
|
||
|
|
||
|
ret = -ENOTSUPP;
|
||
|
if (!ctlr->params.has_ext_regs)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -EINVAL;
|
||
|
if (ctlr->state != CPDMA_STATE_ACTIVE)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -ENOENT;
|
||
|
if (control < 0 || control >= ARRAY_SIZE(controls))
|
||
|
goto unlock_ret;
|
||
|
|
||
|
ret = -EPERM;
|
||
|
if ((info->access & ACCESS_WO) != ACCESS_WO)
|
||
|
goto unlock_ret;
|
||
|
|
||
|
val = dma_reg_read(ctlr, info->reg);
|
||
|
val &= ~(info->mask << info->shift);
|
||
|
val |= (value & info->mask) << info->shift;
|
||
|
dma_reg_write(ctlr, info->reg, val);
|
||
|
ret = 0;
|
||
|
|
||
|
unlock_ret:
|
||
|
spin_unlock_irqrestore(&ctlr->lock, flags);
|
||
|
return ret;
|
||
|
}
|