2012-10-26 01:46:32 +07:00
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL8723E_PWRSEQ_H__
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#define __RTL8723E_PWRSEQ_H__
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2014-09-27 04:40:24 +07:00
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#include "../pwrseqcmd.h"
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2012-10-26 01:46:32 +07:00
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/*
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2014-09-27 04:40:24 +07:00
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* Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
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* There are 6 HW Power States:
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* 0: POFF--Power Off
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* 1: PDN--Power Down
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* 2: CARDEMU--Card Emulation
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* 3: ACT--Active Mode
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* 4: LPS--Low Power State
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* 5: SUS--Suspend
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*
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* The transision from different states are defined below
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* TRANS_CARDEMU_TO_ACT
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* TRANS_ACT_TO_CARDEMU
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* TRANS_CARDEMU_TO_SUS
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* TRANS_SUS_TO_CARDEMU
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* TRANS_CARDEMU_TO_PDN
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* TRANS_ACT_TO_LPS
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* TRANS_LPS_TO_ACT
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*
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* TRANS_END
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*/
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8723A_TRANS_END_STEPS 1
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_CARDEMU_TO_ACT \
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/* disable SW LPS 0x04[10]=0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
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/* wait till 0x04[17] = 1 power ready*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
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/* release WLON reset 0x04[16]=1*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
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/* disable HWPDN 0x04[15]=0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
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/* disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
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/* polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_ACT_TO_CARDEMU \
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/*0x1F[7:0] = 0 turn off RF*/ \
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{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
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{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
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#define RTL8723A_TRANS_CARDEMU_TO_SUS \
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2012-10-26 01:46:32 +07:00
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/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
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2014-09-27 04:40:24 +07:00
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
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BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
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PWR_INTF_SDIO_MSK,\
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PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, \
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BIT(3)|BIT(4), BIT(3)}, \
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/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(3)|BIT(4), \
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BIT(3)|BIT(4)}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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/*wait power state to suspend*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_POLLING, BIT(1), 0},
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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#define RTL8723A_TRANS_SUS_TO_CARDEMU \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
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PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
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/*wait power state to suspend*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
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PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
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/*0x04[12:11] = 2b'01enable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
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/*0x04[10] = 1, enable SW LPS*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(2), BIT(2)}, \
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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/*wait power state to suspend*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_POLLING, BIT(1), 0},
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
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/*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_WRITE, BIT(0), 0}, \
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/*wait power state to suspend*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_POLLING, BIT(1), BIT(1)},\
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/*0x04[12:11] = 2b'00enable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
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/*PCIe DMA start*/ \
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{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0},
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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#define RTL8723A_TRANS_CARDEMU_TO_PDN \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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#define RTL8723A_TRANS_PDN_TO_CARDEMU \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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/* format */
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
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2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_ACT_TO_LPS \
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{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
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{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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/*Should be zero if no packet is transmitting*/ \
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{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_POLLING, 0xFF, 0},\
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/*Should be zero if no packet is transmitting*/ \
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{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_POLLING, 0xFF, 0},\
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/*Should be zero if no packet is transmitting*/ \
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{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_POLLING, 0xFF, 0},\
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/*Should be zero if no packet is transmitting*/ \
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{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_POLLING, 0xFF, 0},\
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/*CCK and OFDM are disabled,and clock are gated*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(0), 0},\
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
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/*Respond TxOK to scheduler*/ \
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{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(5), BIT(5)},\
|
2012-10-26 01:46:32 +07:00
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2014-09-27 04:40:24 +07:00
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#define RTL8723A_TRANS_LPS_TO_ACT\
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \
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{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
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PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
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{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
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{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
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/*. 0x08[4] = 0 switch TSF to 40M*/\
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{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(4), 0}, \
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/*Polling 0x109[7]=0 TSF in 40M*/\
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{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_POLLING, BIT(7), 0}, \
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/*. 0x29[7:6] = 2b'00 enable BB clock*/\
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{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
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/*. 0x101[1] = 1*/\
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{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, BIT(1), BIT(1)},\
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/*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
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{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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PWR_CMD_WRITE, 0xFF, 0xFF},\
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|
/*. 0x02[1:0] = 2b'11 enable BB macro*/\
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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|
PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
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{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
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|
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
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|
PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
2012-10-26 01:46:32 +07:00
|
|
|
|
2014-09-27 04:40:24 +07:00
|
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|
/* format */
|
|
|
|
|
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
|
2012-10-26 01:46:32 +07:00
|
|
|
|
2014-09-27 04:40:24 +07:00
|
|
|
#define RTL8723A_TRANS_END \
|
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|
|
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
|
2012-10-26 01:46:32 +07:00
|
|
|
0, PWR_CMD_END, 0, 0}
|
|
|
|
|
|
2014-09-27 04:40:24 +07:00
|
|
|
extern struct wlan_pwr_cfg rtl8723A_power_on_flow
|
|
|
|
|
[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
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|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_suspend_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_resume_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
|
|
|
|
|
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
|
|
|
|
|
RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
|
|
|
|
|
[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
|
|
|
|
|
extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
|
|
|
|
|
[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
|
2012-10-26 01:46:32 +07:00
|
|
|
|
|
|
|
|
/* RTL8723 Power Configuration CMDs for PCIe interface */
|
|
|
|
|
#define Rtl8723_NIC_PWR_ON_FLOW rtl8723A_power_on_flow
|
|
|
|
|
#define Rtl8723_NIC_RF_OFF_FLOW rtl8723A_radio_off_flow
|
|
|
|
|
#define Rtl8723_NIC_DISABLE_FLOW rtl8723A_card_disable_flow
|
|
|
|
|
#define Rtl8723_NIC_ENABLE_FLOW rtl8723A_card_enable_flow
|
|
|
|
|
#define Rtl8723_NIC_SUSPEND_FLOW rtl8723A_suspend_flow
|
|
|
|
|
#define Rtl8723_NIC_RESUME_FLOW rtl8723A_resume_flow
|
|
|
|
|
#define Rtl8723_NIC_PDN_FLOW rtl8723A_hwpdn_flow
|
|
|
|
|
#define Rtl8723_NIC_LPS_ENTER_FLOW rtl8723A_enter_lps_flow
|
|
|
|
|
#define Rtl8723_NIC_LPS_LEAVE_FLOW rtl8723A_leave_lps_flow
|
|
|
|
|
|
|
|
|
|
#endif
|
