mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 10:45:09 +07:00
198 lines
6.0 KiB
C
198 lines
6.0 KiB
C
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#include <linux/atomic.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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/* Register offsets */
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#define SW_TWSI 0x00
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#define TWSI_INT 0x10
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#define SW_TWSI_EXT 0x18
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/* Controller command patterns */
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#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
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#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
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#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
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#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
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#define SW_TWSI_SIZE_SHIFT 52
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#define SW_TWSI_ADDR_SHIFT 40
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#define SW_TWSI_IA_SHIFT 32 /* Internal address */
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/* Controller opcode word (bits 60:57) */
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#define SW_TWSI_OP_SHIFT 57
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#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
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/* Controller extended opcode word (bits 34:32) */
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#define SW_TWSI_EOP_SHIFT 32
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#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
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/* Controller command and status bits */
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#define TWSI_CTL_CE 0x80 /* High level controller enable */
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#define TWSI_CTL_ENAB 0x40 /* Bus enable */
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#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
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#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
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#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
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#define TWSI_CTL_AAK 0x04 /* Assert ACK */
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/* Status values */
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#define STAT_ERROR 0x00
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#define STAT_START 0x08
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#define STAT_REP_START 0x10
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#define STAT_TXADDR_ACK 0x18
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#define STAT_TXADDR_NAK 0x20
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#define STAT_TXDATA_ACK 0x28
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#define STAT_TXDATA_NAK 0x30
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#define STAT_LOST_ARB_38 0x38
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#define STAT_RXADDR_ACK 0x40
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#define STAT_RXADDR_NAK 0x48
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#define STAT_RXDATA_ACK 0x50
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#define STAT_RXDATA_NAK 0x58
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#define STAT_SLAVE_60 0x60
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#define STAT_LOST_ARB_68 0x68
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#define STAT_SLAVE_70 0x70
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#define STAT_LOST_ARB_78 0x78
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#define STAT_SLAVE_80 0x80
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#define STAT_SLAVE_88 0x88
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#define STAT_GENDATA_ACK 0x90
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#define STAT_GENDATA_NAK 0x98
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#define STAT_SLAVE_A0 0xA0
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#define STAT_SLAVE_A8 0xA8
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#define STAT_LOST_ARB_B0 0xB0
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#define STAT_SLAVE_LOST 0xB8
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#define STAT_SLAVE_NAK 0xC0
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#define STAT_SLAVE_ACK 0xC8
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#define STAT_AD2W_ACK 0xD0
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#define STAT_AD2W_NAK 0xD8
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#define STAT_IDLE 0xF8
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/* TWSI_INT values */
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#define TWSI_INT_ST_INT BIT_ULL(0)
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#define TWSI_INT_TS_INT BIT_ULL(1)
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#define TWSI_INT_CORE_INT BIT_ULL(2)
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#define TWSI_INT_ST_EN BIT_ULL(4)
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#define TWSI_INT_TS_EN BIT_ULL(5)
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#define TWSI_INT_CORE_EN BIT_ULL(6)
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#define TWSI_INT_SDA_OVR BIT_ULL(8)
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#define TWSI_INT_SCL_OVR BIT_ULL(9)
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#define TWSI_INT_SDA BIT_ULL(10)
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#define TWSI_INT_SCL BIT_ULL(11)
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#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
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struct octeon_i2c {
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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int hlc_irq; /* For cn7890 only */
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u32 twsi_freq;
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int sys_freq;
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void __iomem *twsi_base;
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struct device *dev;
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bool hlc_enabled;
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bool broken_irq_mode;
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bool broken_irq_check;
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void (*int_enable)(struct octeon_i2c *);
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void (*int_disable)(struct octeon_i2c *);
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void (*hlc_int_enable)(struct octeon_i2c *);
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void (*hlc_int_disable)(struct octeon_i2c *);
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atomic_t int_enable_cnt;
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atomic_t hlc_int_enable_cnt;
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};
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static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
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{
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__raw_writeq(val, addr);
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__raw_readq(addr); /* wait for write to land */
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}
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/**
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* octeon_i2c_reg_write - write an I2C core register
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* @i2c: The struct octeon_i2c
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* @eop_reg: Register selector
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* @data: Value to be written
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
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{
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u64 tmp;
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__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
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} while ((tmp & SW_TWSI_V) != 0);
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}
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#define octeon_i2c_ctl_write(i2c, val) \
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octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
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#define octeon_i2c_data_write(i2c, val) \
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octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
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/**
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* octeon_i2c_reg_read - read lower bits of an I2C core register
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* @i2c: The struct octeon_i2c
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* @eop_reg: Register selector
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*
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* Returns the data.
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
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{
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u64 tmp;
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__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
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} while ((tmp & SW_TWSI_V) != 0);
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return tmp & 0xFF;
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}
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#define octeon_i2c_ctl_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
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#define octeon_i2c_data_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
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#define octeon_i2c_stat_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
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/**
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* octeon_i2c_read_int - read the TWSI_INT register
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* @i2c: The struct octeon_i2c
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*
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* Returns the value of the register.
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*/
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static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
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{
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return __raw_readq(i2c->twsi_base + TWSI_INT);
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}
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/**
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* octeon_i2c_write_int - write the TWSI_INT register
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* @i2c: The struct octeon_i2c
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* @data: Value to be written
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*/
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static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
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{
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octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
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}
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/* Prototypes */
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irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
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int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
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int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
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void octeon_i2c_set_clock(struct octeon_i2c *i2c);
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extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;
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