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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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64 lines
3.6 KiB
C
64 lines
3.6 KiB
C
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/*
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* File: linux/drivers/serial/bfin_sport_uart.h
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*
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* Based on: include/asm-blackfin/mach-533/bfin_serial_5xx.h
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* Author: Roy Huang <roy.huang>analog.com>
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*
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* Created: Nov 22, 2006
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* Copyright: (C) Analog Device Inc.
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* Description: this driver enable SPORTs on Blackfin emulate UART.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
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#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
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#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
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#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
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#define OFFSET_TX 0x10 /* Transmit Data Register */
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#define OFFSET_RX 0x18 /* Receive Data Register */
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#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
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#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
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#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
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#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
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#define OFFSET_STAT 0x30 /* Status Register */
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#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
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#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
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#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
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#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
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#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
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#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
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#define SPORT_GET_RX32(sport) bfin_read32(((sport)->port.membase + OFFSET_RX))
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#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
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#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
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#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
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#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
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#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
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#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
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#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
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#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
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#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
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#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
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#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
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#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
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#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
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#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
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#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
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#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
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