AuxXxilium/linux_dsm_epyc7002
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linux_dsm_epyc7002/arch/arm/mach-omap2/omap54xx.h

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ARM: OMAP5: Add minimal support for OMAP5430 SOC OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2012-06-05 17:51:32 +07:00
/*:
* Address mappings and base address for OMAP5 interconnects
* and peripherals.
*
* Copyright (C) 2012 Texas Instruments
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_SOC_OMAP54XX_H
#define __ASM_SOC_OMAP54XX_H
/*
* Please place only base defines here and put the rest in device
* specific headers.
*/
#define L4_54XX_BASE 0x4a000000
#define L4_WK_54XX_BASE 0x4ae00000
#define L4_PER_54XX_BASE 0x48000000
#define L3_54XX_BASE 0x44000000
#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
#define OMAP54XX_CM_CORE_BASE 0x4a008000
#define OMAP54XX_PRM_BASE 0x4ae06000
#define OMAP54XX_PRCM_MPU_BASE 0x48243000
#define OMAP54XX_SCM_BASE 0x4a002000
#define OMAP54XX_CTRL_BASE 0x4a002800
ARM: OMAP5: Update SAR RAM base address Update SAR RAM base address for OMAP5 based devices. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-02-06 19:24:39 +07:00
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
ARM: OMAP5: Add minimal support for OMAP5430 SOC OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2012-06-05 17:51:32 +07:00
ARM: DRA7: Provide proper IO map table DRA7 uses OMAP5 IO table at the moment. This is purely spurious since the OMAP5 and DRA7 register maps are different in many aspects. AM57xx/DRA7 TRM Reference: http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf NOTE: Most of the drivers are already doing ioremap, so, there should'nt be any functional improvement involved here, other than making the initial iotable more accurate. Fixes: a3a9384a1157 ("ARM: DRA7: Reuse io tables and add a new .init_early") Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-06-22 22:12:14 +07:00
/* DRA7 specific base addresses */
#define L3_MAIN_SN_DRA7XX_BASE 0x44000000
#define L4_PER1_DRA7XX_BASE 0x48000000
#define L4_CFG_MPU_DRA7XX_BASE 0x48210000
#define L4_PER2_DRA7XX_BASE 0x48400000
#define L4_PER3_DRA7XX_BASE 0x48800000
#define L4_CFG_DRA7XX_BASE 0x4A000000
#define L4_WKUP_DRA7XX_BASE 0x4ae00000
ARM: DRA7: Reuse io tables and add a new .init_early The IO descriptor tables for DRA7 are a complete reuse from OMAP5. A new dra7xx_init_early() does the base address inits. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-07-03 13:22:04 +07:00
#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
#define DRA7XX_CTRL_BASE 0x4a003400
#define DRA7XX_TAP_BASE 0x4ae0c000
ARM: OMAP5: Add minimal support for OMAP5430 SOC OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2012-06-05 17:51:32 +07:00
#endif /* __ASM_SOC_OMAP555554XX_H */
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