License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 05:20:36 +07:00
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/*
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* linux/arch/alpha/kernel/sys_cabriolet.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999, 2000 Richard Henderson
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*
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* Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
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* PC164 and LX164.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_apecs.h>
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#include <asm/core_cia.h>
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#include <asm/core_lca.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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2010-09-01 09:29:13 +07:00
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#include "pc873xx.h"
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2005-04-17 05:20:36 +07:00
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/* Note mask bit is true for DISABLED irqs. */
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static unsigned long cached_irq_mask = ~0UL;
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static inline void
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cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
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{
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int ofs = (irq - 16) / 8;
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outb(mask >> (16 + ofs * 8), 0x804 + ofs);
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}
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static inline void
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2011-02-06 21:32:30 +07:00
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cabriolet_enable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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2011-02-06 21:32:30 +07:00
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cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
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2005-04-17 05:20:36 +07:00
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}
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static void
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2011-02-06 21:32:30 +07:00
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cabriolet_disable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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2011-02-06 21:32:30 +07:00
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cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
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2005-04-17 05:20:36 +07:00
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}
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2009-06-17 05:33:25 +07:00
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static struct irq_chip cabriolet_irq_type = {
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2009-12-01 10:51:31 +07:00
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.name = "CABRIOLET",
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2011-02-06 21:32:30 +07:00
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.irq_unmask = cabriolet_enable_irq,
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.irq_mask = cabriolet_disable_irq,
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.irq_mask_ack = cabriolet_disable_irq,
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2005-04-17 05:20:36 +07:00
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};
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static void
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2006-10-08 20:36:08 +07:00
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cabriolet_device_interrupt(unsigned long v)
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2005-04-17 05:20:36 +07:00
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{
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unsigned long pld;
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unsigned int i;
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/* Read the interrupt summary registers */
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pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i == 4) {
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2006-10-08 20:36:08 +07:00
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isa_device_interrupt(v);
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2005-04-17 05:20:36 +07:00
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} else {
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2006-10-08 20:37:32 +07:00
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handle_irq(16 + i);
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2005-04-17 05:20:36 +07:00
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}
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}
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}
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static void __init
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2006-10-08 20:36:08 +07:00
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common_init_irq(void (*srm_dev_int)(unsigned long v))
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2005-04-17 05:20:36 +07:00
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{
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init_i8259a_irqs();
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if (alpha_using_srm) {
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alpha_mv.device_interrupt = srm_dev_int;
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init_srm_irqs(35, 0);
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}
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else {
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long i;
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outb(0xff, 0x804);
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outb(0xff, 0x805);
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outb(0xff, 0x806);
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for (i = 16; i < 35; ++i) {
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2011-03-26 04:17:31 +07:00
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irq_set_chip_and_handler(i, &cabriolet_irq_type,
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handle_level_irq);
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2011-02-06 21:32:30 +07:00
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irq_set_status_flags(i, IRQ_LEVEL);
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2005-04-17 05:20:36 +07:00
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}
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}
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common_init_isa_dma();
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setup_irq(16+4, &isa_cascade_irqaction);
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}
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#ifndef CONFIG_ALPHA_PC164
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static void __init
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cabriolet_init_irq(void)
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{
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common_init_irq(srm_device_interrupt);
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}
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
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/* In theory, the PC164 has the same interrupt hardware as the other
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Cabriolet based systems. However, something got screwed up late
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in the development cycle which broke the interrupt masking hardware.
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Repeat, it is not possible to mask and ack interrupts. At all.
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In an attempt to work around this, while processing interrupts,
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we do not allow the IPL to drop below what it is currently. This
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prevents the possibility of recursion.
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??? Another option might be to force all PCI devices to use edge
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triggered rather than level triggered interrupts. That might be
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too invasive though. */
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static void
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2006-10-08 20:36:08 +07:00
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pc164_srm_device_interrupt(unsigned long v)
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2005-04-17 05:20:36 +07:00
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{
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__min_ipl = getipl();
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2006-10-08 20:36:08 +07:00
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srm_device_interrupt(v);
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2005-04-17 05:20:36 +07:00
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__min_ipl = 0;
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}
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static void
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2006-10-08 20:36:08 +07:00
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pc164_device_interrupt(unsigned long v)
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2005-04-17 05:20:36 +07:00
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{
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__min_ipl = getipl();
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2006-10-08 20:36:08 +07:00
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cabriolet_device_interrupt(v);
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2005-04-17 05:20:36 +07:00
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__min_ipl = 0;
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}
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static void __init
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pc164_init_irq(void)
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{
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common_init_irq(pc164_srm_device_interrupt);
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}
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#endif
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/*
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* The EB66+ is very similar to the EB66 except that it does not have
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* the on-board NCR and Tulip chips. In the code below, I have used
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* slot number to refer to the id select line and *not* the slot
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* number used in the EB66+ documentation. However, in the table,
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* I've given the slot number, the id select line and the Jxx number
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* that's printed on the board. The interrupt pins from the PCI slots
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* are wired into 3 interrupt summary registers at 0x804, 0x805 and
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* 0x806 ISA.
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*
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* In the table, -1 means don't assign an IRQ number. This is usually
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* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
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*/
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2017-10-26 21:54:15 +07:00
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static inline int
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2011-06-10 21:30:21 +07:00
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eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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2005-04-17 05:20:36 +07:00
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{
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2017-10-26 21:54:15 +07:00
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static char irq_tab[5][5] = {
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2005-04-17 05:20:36 +07:00
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/*INT INTA INTB INTC INTD */
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{16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
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{16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
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{16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
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{16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
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};
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const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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/*
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* The AlphaPC64 is very similar to the EB66+ except that its slots
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* are numbered differently. In the code below, I have used slot
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* number to refer to the id select line and *not* the slot number
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* used in the AlphaPC64 documentation. However, in the table, I've
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* given the slot number, the id select line and the Jxx number that's
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* printed on the board. The interrupt pins from the PCI slots are
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* wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
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* ISA.
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*
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* In the table, -1 means don't assign an IRQ number. This is usually
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* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
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*/
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2017-10-26 21:54:15 +07:00
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static inline int
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2011-06-10 21:30:21 +07:00
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cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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2005-04-17 05:20:36 +07:00
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{
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2017-10-26 21:54:15 +07:00
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static char irq_tab[5][5] = {
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2005-04-17 05:20:36 +07:00
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/*INT INTA INTB INTC INTD */
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{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
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{ 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
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{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
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{ 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
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};
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const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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2010-09-01 09:29:13 +07:00
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static inline void __init
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cabriolet_enable_ide(void)
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{
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if (pc873xx_probe() == -1) {
|
|
|
|
|
printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
|
|
|
|
|
} else {
|
|
|
|
|
printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
|
|
|
|
|
pc873xx_get_model(), pc873xx_get_base());
|
|
|
|
|
|
|
|
|
|
pc873xx_enable_ide();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
static inline void __init
|
|
|
|
|
cabriolet_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
common_init_pci();
|
2010-09-01 09:29:13 +07:00
|
|
|
cabriolet_enable_ide();
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void __init
|
|
|
|
|
cia_cab_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
cia_init_pci();
|
2010-09-01 09:29:13 +07:00
|
|
|
cabriolet_enable_ide();
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The PC164 and LX164 have 19 PCI interrupts, four from each of the four
|
|
|
|
|
* PCI slots, the SIO, PCI/IDE, and USB.
|
|
|
|
|
*
|
|
|
|
|
* Each of the interrupts can be individually masked. This is
|
|
|
|
|
* accomplished by setting the appropriate bit in the mask register.
|
|
|
|
|
* A bit is set by writing a "1" to the desired position in the mask
|
|
|
|
|
* register and cleared by writing a "0". There are 3 mask registers
|
|
|
|
|
* located at ISA address 804h, 805h and 806h.
|
|
|
|
|
*
|
|
|
|
|
* An I/O read at ISA address 804h, 805h, 806h will return the
|
|
|
|
|
* state of the 11 PCI interrupts and not the state of the MASKED
|
|
|
|
|
* interrupts.
|
|
|
|
|
*
|
|
|
|
|
* Note: A write to I/O 804h, 805h, and 806h the mask register will be
|
|
|
|
|
* updated.
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* ISA DATA<7:0>
|
|
|
|
|
* ISA +--------------------------------------------------------------+
|
|
|
|
|
* ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|
|
|
* +==============================================================+
|
|
|
|
|
* 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
|
|
|
|
|
* +--------------------------------------------------------------+
|
|
|
|
|
* 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
|
|
|
|
|
* +--------------------------------------------------------------+
|
|
|
|
|
* 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 |
|
|
|
|
|
* +--------------------------------------------------------------+
|
|
|
|
|
* * Rsrv = reserved bits
|
|
|
|
|
* Note: The mask register is write-only.
|
|
|
|
|
*
|
|
|
|
|
* IdSel
|
|
|
|
|
* 5 32 bit PCI option slot 2
|
|
|
|
|
* 6 64 bit PCI option slot 0
|
|
|
|
|
* 7 64 bit PCI option slot 1
|
|
|
|
|
* 8 Saturn I/O
|
|
|
|
|
* 9 32 bit PCI option slot 3
|
|
|
|
|
* 10 USB
|
|
|
|
|
* 11 IDE
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static inline int
|
2011-06-10 21:30:21 +07:00
|
|
|
alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2017-10-26 21:54:15 +07:00
|
|
|
static char irq_tab[7][5] = {
|
2005-04-17 05:20:36 +07:00
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
|
|
|
|
|
{ 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
|
|
|
|
|
{ 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
|
|
|
|
|
{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
|
|
|
|
|
{ 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
|
|
|
|
|
{ 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
|
|
|
|
|
};
|
|
|
|
|
const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
|
|
|
|
|
return COMMON_TABLE_LOOKUP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void __init
|
|
|
|
|
alphapc164_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
cia_init_pci();
|
|
|
|
|
SMC93x_Init();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vector
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
|
|
|
|
|
struct alpha_machine_vector cabriolet_mv __initmv = {
|
|
|
|
|
.vector_name = "Cabriolet",
|
|
|
|
|
DO_EV4_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_APECS_IO,
|
|
|
|
|
.machine_check = apecs_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 35,
|
|
|
|
|
.device_interrupt = cabriolet_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = apecs_init_arch,
|
|
|
|
|
.init_irq = cabriolet_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = cabriolet_init_pci,
|
|
|
|
|
.pci_map_irq = cabriolet_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
#ifndef CONFIG_ALPHA_EB64P
|
|
|
|
|
ALIAS_MV(cabriolet)
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
|
|
|
|
|
struct alpha_machine_vector eb164_mv __initmv = {
|
|
|
|
|
.vector_name = "EB164",
|
|
|
|
|
DO_EV5_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_CIA_IO,
|
|
|
|
|
.machine_check = cia_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = CIA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 35,
|
|
|
|
|
.device_interrupt = cabriolet_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = cia_init_arch,
|
|
|
|
|
.init_irq = cabriolet_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = cia_cab_init_pci,
|
|
|
|
|
.kill_arch = cia_kill_arch,
|
|
|
|
|
.pci_map_irq = cabriolet_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(eb164)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
|
|
|
|
|
struct alpha_machine_vector eb66p_mv __initmv = {
|
|
|
|
|
.vector_name = "EB66+",
|
|
|
|
|
DO_EV4_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_LCA_IO,
|
|
|
|
|
.machine_check = lca_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 35,
|
|
|
|
|
.device_interrupt = cabriolet_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = lca_init_arch,
|
|
|
|
|
.init_irq = cabriolet_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = cabriolet_init_pci,
|
|
|
|
|
.pci_map_irq = eb66p_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(eb66p)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
|
|
|
|
|
struct alpha_machine_vector lx164_mv __initmv = {
|
|
|
|
|
.vector_name = "LX164",
|
|
|
|
|
DO_EV5_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_PYXIS_IO,
|
|
|
|
|
.machine_check = cia_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = PYXIS_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 35,
|
|
|
|
|
.device_interrupt = cabriolet_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = pyxis_init_arch,
|
|
|
|
|
.init_irq = cabriolet_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = alphapc164_init_pci,
|
|
|
|
|
.kill_arch = cia_kill_arch,
|
|
|
|
|
.pci_map_irq = alphapc164_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(lx164)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
|
|
|
|
|
struct alpha_machine_vector pc164_mv __initmv = {
|
|
|
|
|
.vector_name = "PC164",
|
|
|
|
|
DO_EV5_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_CIA_IO,
|
|
|
|
|
.machine_check = cia_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = CIA_DEFAULT_MEM_BASE,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 35,
|
|
|
|
|
.device_interrupt = pc164_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = cia_init_arch,
|
|
|
|
|
.init_irq = pc164_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = alphapc164_init_pci,
|
|
|
|
|
.kill_arch = cia_kill_arch,
|
|
|
|
|
.pci_map_irq = alphapc164_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(pc164)
|
|
|
|
|
#endif
|