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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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232 lines
6.0 KiB
C
232 lines
6.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, Linaro Limited
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* Author: Georgi Djakov <georgi.djakov@linaro.org>
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/regmap.h>
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#include "clk-regmap-mux-div.h"
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#define CMD_RCGR 0x0
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#define CMD_RCGR_UPDATE BIT(0)
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#define CMD_RCGR_DIRTY_CFG BIT(4)
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#define CMD_RCGR_ROOT_OFF BIT(31)
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#define CFG_RCGR 0x4
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#define to_clk_regmap_mux_div(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
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int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
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{
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int ret, count;
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u32 val, mask;
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const char *name = clk_hw_get_name(&md->clkr.hw);
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val = (div << md->hid_shift) | (src << md->src_shift);
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mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
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((BIT(md->src_width) - 1) << md->src_shift);
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ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
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mask, val);
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if (ret)
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return ret;
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ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
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CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
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if (ret)
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return ret;
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/* Wait for update to take effect */
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for (count = 500; count > 0; count--) {
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ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
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&val);
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if (ret)
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return ret;
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if (!(val & CMD_RCGR_UPDATE))
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return 0;
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udelay(1);
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}
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pr_err("%s: RCG did not update its configuration", name);
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return -EBUSY;
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}
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EXPORT_SYMBOL_GPL(mux_div_set_src_div);
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static void mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
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u32 *div)
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{
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u32 val, d, s;
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const char *name = clk_hw_get_name(&md->clkr.hw);
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regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
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if (val & CMD_RCGR_DIRTY_CFG) {
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pr_err("%s: RCG configuration is pending\n", name);
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return;
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}
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regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
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s = (val >> md->src_shift);
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s &= BIT(md->src_width) - 1;
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*src = s;
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d = (val >> md->hid_shift);
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d &= BIT(md->hid_width) - 1;
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*div = d;
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}
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static inline bool is_better_rate(unsigned long req, unsigned long best,
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unsigned long new)
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{
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return (req <= new && new < best) || (best < req && best < new);
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}
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static int mux_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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unsigned int i, div, max_div;
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unsigned long actual_rate, best_rate = 0;
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unsigned long req_rate = req->rate;
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
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unsigned long parent_rate = clk_hw_get_rate(parent);
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max_div = BIT(md->hid_width) - 1;
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for (div = 1; div < max_div; div++) {
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parent_rate = mult_frac(req_rate, div, 2);
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parent_rate = clk_hw_round_rate(parent, parent_rate);
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actual_rate = mult_frac(parent_rate, 2, div);
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if (is_better_rate(req_rate, best_rate, actual_rate)) {
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best_rate = actual_rate;
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req->rate = best_rate;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent;
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}
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if (actual_rate < req_rate || best_rate <= req_rate)
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break;
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}
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}
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if (!best_rate)
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return -EINVAL;
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return 0;
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}
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static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long prate, u32 src)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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int ret;
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u32 div, max_div, best_src = 0, best_div = 0;
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unsigned int i;
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unsigned long actual_rate, best_rate = 0;
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
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unsigned long parent_rate = clk_hw_get_rate(parent);
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max_div = BIT(md->hid_width) - 1;
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for (div = 1; div < max_div; div++) {
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parent_rate = mult_frac(rate, div, 2);
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parent_rate = clk_hw_round_rate(parent, parent_rate);
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actual_rate = mult_frac(parent_rate, 2, div);
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if (is_better_rate(rate, best_rate, actual_rate)) {
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best_rate = actual_rate;
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best_src = md->parent_map[i];
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best_div = div - 1;
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}
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if (actual_rate < rate || best_rate <= rate)
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break;
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}
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}
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ret = mux_div_set_src_div(md, best_src, best_div);
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if (!ret) {
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md->div = best_div;
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md->src = best_src;
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}
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return ret;
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}
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static u8 mux_div_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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const char *name = clk_hw_get_name(hw);
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u32 i, div, src = 0;
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mux_div_get_src_div(md, &src, &div);
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for (i = 0; i < clk_hw_get_num_parents(hw); i++)
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if (src == md->parent_map[i])
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return i;
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pr_err("%s: Can't find parent with src %d\n", name, src);
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return 0;
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}
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static int mux_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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return mux_div_set_src_div(md, md->parent_map[index], md->div);
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}
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static int mux_div_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long prate)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
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}
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static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long prate, u8 index)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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return __mux_div_set_rate_and_parent(hw, rate, prate,
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md->parent_map[index]);
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}
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static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
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u32 div, src;
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int i, num_parents = clk_hw_get_num_parents(hw);
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const char *name = clk_hw_get_name(hw);
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mux_div_get_src_div(md, &src, &div);
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for (i = 0; i < num_parents; i++)
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if (src == md->parent_map[i]) {
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struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
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unsigned long parent_rate = clk_hw_get_rate(p);
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return mult_frac(parent_rate, 2, div + 1);
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}
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pr_err("%s: Can't find parent %d\n", name, src);
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return 0;
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}
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const struct clk_ops clk_regmap_mux_div_ops = {
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.get_parent = mux_div_get_parent,
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.set_parent = mux_div_set_parent,
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.set_rate = mux_div_set_rate,
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.set_rate_and_parent = mux_div_set_rate_and_parent,
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.determine_rate = mux_div_determine_rate,
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.recalc_rate = mux_div_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
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