2009-11-25 22:41:04 +07:00
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/*
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* imx-ssi.c -- ALSA Soc Audio Layer
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*
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* Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This code is based on code copyrighted by Freescale,
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* Liam Girdwood, Javier Martin and probably others.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* The i.MX SSI core has some nasty limitations in AC97 mode. While most
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* sane processor vendors have a FIFO per AC97 slot, the i.MX has only
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* one FIFO which combines all valid receive slots. We cannot even select
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* which slots we want to receive. The WM9712 with which this driver
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2011-03-31 08:57:33 +07:00
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* was developed with always sends GPIO status data in slot 12 which
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2009-11-25 22:41:04 +07:00
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* we receive in our (PCM-) data stream. The only chance we have is to
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* manually skip this data in the FIQ handler. With sampling rates different
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* from 48000Hz not every frame has valid receive data, so the ratio
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* between pcm data and GPIO status data changes. Our FIQ handler is not
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* able to handle this, hence this driver only works with 48000Hz sampling
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* rate.
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2010-07-13 16:27:58 +07:00
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* Reading and writing AC97 registers is another challenge. The core
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2009-11-25 22:41:04 +07:00
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* provides us status bits when the read register is updated with *another*
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* value. When we read the same register two times (and the register still
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* contains the same value) these status bits are not set. We work
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* around this by not polling these bits but only wait a fixed delay.
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2012-03-16 15:56:38 +07:00
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*
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2009-11-25 22:41:04 +07:00
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2009-11-25 22:41:04 +07:00
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#include <sound/core.h>
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#include <sound/initval.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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2012-08-24 20:14:29 +07:00
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#include <linux/platform_data/asoc-imx-ssi.h>
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2009-11-25 22:41:04 +07:00
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#include "imx-ssi.h"
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2014-03-21 13:17:15 +07:00
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#include "fsl_utils.h"
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2009-11-25 22:41:04 +07:00
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#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
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/*
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* SSI Network Mode or TDM slots configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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*/
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static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
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unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
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{
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2010-03-18 03:15:21 +07:00
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struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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2009-11-25 22:41:04 +07:00
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u32 sccr;
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sccr = readl(ssi->base + SSI_STCCR);
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sccr &= ~SSI_STCCR_DC_MASK;
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sccr |= SSI_STCCR_DC(slots - 1);
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writel(sccr, ssi->base + SSI_STCCR);
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sccr = readl(ssi->base + SSI_SRCCR);
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sccr &= ~SSI_STCCR_DC_MASK;
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sccr |= SSI_STCCR_DC(slots - 1);
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writel(sccr, ssi->base + SSI_SRCCR);
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2015-01-12 16:27:18 +07:00
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writel(~tx_mask, ssi->base + SSI_STMSK);
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writel(~rx_mask, ssi->base + SSI_SRMSK);
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2009-11-25 22:41:04 +07:00
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return 0;
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}
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/*
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* SSI DAI format configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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*/
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static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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2010-03-18 03:15:21 +07:00
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struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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2009-11-25 22:41:04 +07:00
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u32 strcr = 0, scr;
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scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
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/* DAI mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* data on rising edge of bclk, frame low 1clk before data */
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strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
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scr |= SSI_SCR_NET;
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2010-05-27 15:58:54 +07:00
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if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
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scr &= ~SSI_I2S_MODE_MASK;
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scr |= SSI_SCR_I2S_MODE_SLAVE;
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}
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2009-11-25 22:41:04 +07:00
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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/* data on rising edge of bclk, frame high with data */
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strcr |= SSI_STCR_TXBIT0;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* data on rising edge of bclk, frame high with data */
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2011-03-01 21:02:06 +07:00
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strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
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2009-11-25 22:41:04 +07:00
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/* data on rising edge of bclk, frame high 1clk before data */
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2012-02-23 21:43:18 +07:00
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strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
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2009-11-25 22:41:04 +07:00
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break;
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}
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/* DAI clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_IF:
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strcr |= SSI_STCR_TFSI;
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strcr &= ~SSI_STCR_TSCKP;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
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break;
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case SND_SOC_DAIFMT_NB_IF:
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strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
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break;
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case SND_SOC_DAIFMT_NB_NF:
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strcr &= ~SSI_STCR_TFSI;
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strcr |= SSI_STCR_TSCKP;
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break;
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}
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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2010-01-11 23:56:19 +07:00
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case SND_SOC_DAIFMT_CBM_CFM:
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2009-11-25 22:41:04 +07:00
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break;
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2010-01-11 23:56:19 +07:00
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default:
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/* Master mode not implemented, needs handling of clocks. */
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return -EINVAL;
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2009-11-25 22:41:04 +07:00
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}
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strcr |= SSI_STCR_TFEN0;
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2010-05-27 15:58:54 +07:00
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if (ssi->flags & IMX_SSI_NET)
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scr |= SSI_SCR_NET;
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if (ssi->flags & IMX_SSI_SYN)
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scr |= SSI_SCR_SYN;
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2009-11-25 22:41:04 +07:00
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writel(strcr, ssi->base + SSI_STCR);
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writel(strcr, ssi->base + SSI_SRCR);
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writel(scr, ssi->base + SSI_SCR);
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return 0;
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}
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/*
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* SSI system clock configuration.
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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*/
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static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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2010-03-18 03:15:21 +07:00
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struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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2009-11-25 22:41:04 +07:00
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u32 scr;
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scr = readl(ssi->base + SSI_SCR);
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switch (clk_id) {
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case IMX_SSP_SYS_CLK:
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if (dir == SND_SOC_CLOCK_OUT)
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scr |= SSI_SCR_SYS_CLK_EN;
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else
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scr &= ~SSI_SCR_SYS_CLK_EN;
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break;
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default:
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return -EINVAL;
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}
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writel(scr, ssi->base + SSI_SCR);
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return 0;
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}
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/*
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* SSI Clock dividers
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* Should only be called when port is inactive (i.e. SSIEN = 0).
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*/
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static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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2010-03-18 03:15:21 +07:00
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struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
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2009-11-25 22:41:04 +07:00
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u32 stccr, srccr;
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stccr = readl(ssi->base + SSI_STCCR);
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srccr = readl(ssi->base + SSI_SRCCR);
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switch (div_id) {
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case IMX_SSI_TX_DIV_2:
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stccr &= ~SSI_STCCR_DIV2;
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stccr |= div;
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break;
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case IMX_SSI_TX_DIV_PSR:
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stccr &= ~SSI_STCCR_PSR;
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stccr |= div;
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break;
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case IMX_SSI_TX_DIV_PM:
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stccr &= ~0xff;
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stccr |= SSI_STCCR_PM(div);
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break;
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case IMX_SSI_RX_DIV_2:
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stccr &= ~SSI_STCCR_DIV2;
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stccr |= div;
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break;
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case IMX_SSI_RX_DIV_PSR:
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stccr &= ~SSI_STCCR_PSR;
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stccr |= div;
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break;
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case IMX_SSI_RX_DIV_PM:
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stccr &= ~0xff;
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stccr |= SSI_STCCR_PM(div);
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break;
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default:
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return -EINVAL;
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}
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writel(stccr, ssi->base + SSI_STCCR);
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writel(srccr, ssi->base + SSI_SRCCR);
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return 0;
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}
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/*
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* Should only be called when port is inactive (i.e. SSIEN = 0),
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* although can be called multiple times by upper layers.
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*/
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static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
|
2010-03-18 03:15:21 +07:00
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struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
|
2009-11-25 22:41:04 +07:00
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u32 reg, sccr;
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/* Tx/Rx config */
|
2012-02-22 16:49:05 +07:00
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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2009-11-25 22:41:04 +07:00
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reg = SSI_STCCR;
|
2012-02-22 16:49:05 +07:00
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else
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2009-11-25 22:41:04 +07:00
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reg = SSI_SRCCR;
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2010-08-23 13:54:02 +07:00
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if (ssi->flags & IMX_SSI_SYN)
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reg = SSI_STCCR;
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2009-11-25 22:41:04 +07:00
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sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
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/* DAI data (word) size */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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sccr |= SSI_SRCCR_WL(16);
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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sccr |= SSI_SRCCR_WL(20);
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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sccr |= SSI_SRCCR_WL(24);
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break;
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}
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writel(sccr, ssi->base + reg);
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return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2010-03-18 03:15:21 +07:00
|
|
|
struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2009-11-25 22:41:04 +07:00
|
|
|
unsigned int sier_bits, sier;
|
|
|
|
unsigned int scr;
|
|
|
|
|
|
|
|
scr = readl(ssi->base + SSI_SCR);
|
|
|
|
sier = readl(ssi->base + SSI_SIER);
|
|
|
|
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
if (ssi->flags & IMX_SSI_DMA)
|
|
|
|
sier_bits = SSI_SIER_TDMAE;
|
|
|
|
else
|
|
|
|
sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
|
|
|
|
} else {
|
|
|
|
if (ssi->flags & IMX_SSI_DMA)
|
|
|
|
sier_bits = SSI_SIER_RDMAE;
|
|
|
|
else
|
|
|
|
sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
scr |= SSI_SCR_TE;
|
|
|
|
else
|
|
|
|
scr |= SSI_SCR_RE;
|
|
|
|
sier |= sier_bits;
|
|
|
|
|
2013-11-16 14:52:25 +07:00
|
|
|
scr |= SSI_SCR_SSIEN;
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
scr &= ~SSI_SCR_TE;
|
|
|
|
else
|
|
|
|
scr &= ~SSI_SCR_RE;
|
|
|
|
sier &= ~sier_bits;
|
|
|
|
|
2013-11-16 14:52:25 +07:00
|
|
|
if (!(scr & (SSI_SCR_TE | SSI_SCR_RE)))
|
2009-11-25 22:41:04 +07:00
|
|
|
scr &= ~SSI_SCR_SSIEN;
|
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(ssi->flags & IMX_SSI_USE_AC97))
|
|
|
|
/* rx/tx are always enabled to access ac97 registers */
|
|
|
|
writel(scr, ssi->base + SSI_SCR);
|
|
|
|
|
|
|
|
writel(sier, ssi->base + SSI_SIER);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-23 17:40:40 +07:00
|
|
|
static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
|
2009-11-25 22:41:04 +07:00
|
|
|
.hw_params = imx_ssi_hw_params,
|
|
|
|
.set_fmt = imx_ssi_set_dai_fmt,
|
|
|
|
.set_clkdiv = imx_ssi_set_dai_clkdiv,
|
|
|
|
.set_sysclk = imx_ssi_set_dai_sysclk,
|
|
|
|
.set_tdm_slot = imx_ssi_set_dai_tdm_slot,
|
|
|
|
.trigger = imx_ssi_trigger,
|
|
|
|
};
|
|
|
|
|
2010-11-04 23:05:42 +07:00
|
|
|
static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
snd_soc_dai_set_drvdata(dai, ssi);
|
|
|
|
|
2013-04-03 16:06:04 +07:00
|
|
|
val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) |
|
|
|
|
SSI_SFCSR_RFWM0(ssi->dma_params_rx.maxburst);
|
2010-11-04 23:05:42 +07:00
|
|
|
writel(val, ssi->base + SSI_SFCSR);
|
|
|
|
|
2013-04-16 00:19:58 +07:00
|
|
|
/* Tx/Rx config */
|
|
|
|
dai->playback_dma_data = &ssi->dma_params_tx;
|
|
|
|
dai->capture_dma_data = &ssi->dma_params_rx;
|
|
|
|
|
2010-11-04 23:05:42 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
static struct snd_soc_dai_driver imx_ssi_dai = {
|
2010-11-04 23:05:42 +07:00
|
|
|
.probe = imx_ssi_dai_probe,
|
2010-03-18 03:15:21 +07:00
|
|
|
.playback = {
|
2012-09-06 07:30:10 +07:00
|
|
|
.channels_min = 1,
|
2010-03-18 03:15:21 +07:00
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
2012-09-06 07:30:10 +07:00
|
|
|
.channels_min = 1,
|
2010-03-18 03:15:21 +07:00
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.ops = &imx_ssi_pcm_dai_ops,
|
2009-11-25 22:41:04 +07:00
|
|
|
};
|
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
static struct snd_soc_dai_driver imx_ac97_dai = {
|
|
|
|
.probe = imx_ssi_dai_probe,
|
2014-11-11 04:41:52 +07:00
|
|
|
.bus_control = true,
|
2009-11-25 22:41:04 +07:00
|
|
|
.playback = {
|
|
|
|
.stream_name = "AC97 Playback",
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
2013-03-11 01:33:02 +07:00
|
|
|
.rates = SNDRV_PCM_RATE_8000_48000,
|
2009-11-25 22:41:04 +07:00
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "AC97 Capture",
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
|
|
},
|
|
|
|
.ops = &imx_ssi_pcm_dai_ops,
|
|
|
|
};
|
|
|
|
|
2013-03-21 17:32:15 +07:00
|
|
|
static const struct snd_soc_component_driver imx_component = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
};
|
|
|
|
|
2009-11-25 22:41:04 +07:00
|
|
|
static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
|
|
|
|
{
|
|
|
|
void __iomem *base = imx_ssi->base;
|
|
|
|
|
|
|
|
writel(0x0, base + SSI_SCR);
|
|
|
|
writel(0x0, base + SSI_STCR);
|
|
|
|
writel(0x0, base + SSI_SRCR);
|
|
|
|
|
|
|
|
writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
|
|
|
|
|
|
|
|
writel(SSI_SFCSR_RFWM0(8) |
|
|
|
|
SSI_SFCSR_TFWM0(8) |
|
|
|
|
SSI_SFCSR_RFWM1(8) |
|
|
|
|
SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
|
|
|
|
|
|
|
|
writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
|
|
|
|
writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
|
|
|
|
|
|
|
|
writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
|
|
|
|
writel(SSI_SOR_WAIT(3), base + SSI_SOR);
|
|
|
|
|
|
|
|
writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
|
|
|
|
SSI_SCR_TE | SSI_SCR_RE,
|
|
|
|
base + SSI_SCR);
|
|
|
|
|
|
|
|
writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
|
|
|
|
writel(0xff, base + SSI_SACCDIS);
|
|
|
|
writel(0x300, base + SSI_SACCEN);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct imx_ssi *ac97_ssi;
|
|
|
|
|
|
|
|
static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
|
|
|
unsigned short val)
|
|
|
|
{
|
|
|
|
struct imx_ssi *imx_ssi = ac97_ssi;
|
|
|
|
void __iomem *base = imx_ssi->base;
|
|
|
|
unsigned int lreg;
|
|
|
|
unsigned int lval;
|
|
|
|
|
|
|
|
if (reg > 0x7f)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
|
|
|
|
|
|
|
|
lreg = reg << 12;
|
|
|
|
writel(lreg, base + SSI_SACADD);
|
|
|
|
|
|
|
|
lval = val << 4;
|
|
|
|
writel(lval , base + SSI_SACDAT);
|
|
|
|
|
|
|
|
writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
|
|
|
|
udelay(100);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
|
|
|
|
unsigned short reg)
|
|
|
|
{
|
|
|
|
struct imx_ssi *imx_ssi = ac97_ssi;
|
|
|
|
void __iomem *base = imx_ssi->base;
|
|
|
|
|
|
|
|
unsigned short val = -1;
|
|
|
|
unsigned int lreg;
|
|
|
|
|
|
|
|
lreg = (reg & 0x7f) << 12 ;
|
|
|
|
writel(lreg, base + SSI_SACADD);
|
|
|
|
writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
|
|
|
|
|
|
|
|
pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
|
|
|
|
{
|
|
|
|
struct imx_ssi *imx_ssi = ac97_ssi;
|
|
|
|
|
|
|
|
if (imx_ssi->ac97_reset)
|
|
|
|
imx_ssi->ac97_reset(ac97);
|
2013-03-11 01:33:03 +07:00
|
|
|
/* First read sometimes fails, do a dummy read */
|
|
|
|
imx_ssi_ac97_read(ac97, 0);
|
2009-11-25 22:41:04 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
|
|
|
|
{
|
|
|
|
struct imx_ssi *imx_ssi = ac97_ssi;
|
|
|
|
|
|
|
|
if (imx_ssi->ac97_warm_reset)
|
|
|
|
imx_ssi->ac97_warm_reset(ac97);
|
2013-03-11 01:33:03 +07:00
|
|
|
|
|
|
|
/* First read sometimes fails, do a dummy read */
|
|
|
|
imx_ssi_ac97_read(ac97, 0);
|
2009-11-25 22:41:04 +07:00
|
|
|
}
|
|
|
|
|
2013-06-26 18:45:59 +07:00
|
|
|
static struct snd_ac97_bus_ops imx_ssi_ac97_ops = {
|
2009-11-25 22:41:04 +07:00
|
|
|
.read = imx_ssi_ac97_read,
|
|
|
|
.write = imx_ssi_ac97_write,
|
|
|
|
.reset = imx_ssi_ac97_reset,
|
|
|
|
.warm_reset = imx_ssi_ac97_warm_reset
|
|
|
|
};
|
|
|
|
|
|
|
|
static int imx_ssi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
struct imx_ssi *ssi;
|
|
|
|
struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
|
|
|
|
int ret = 0;
|
2010-03-18 03:15:21 +07:00
|
|
|
struct snd_soc_dai_driver *dai;
|
2009-11-25 22:41:04 +07:00
|
|
|
|
2012-07-28 00:32:10 +07:00
|
|
|
ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
|
2009-11-25 22:41:04 +07:00
|
|
|
if (!ssi)
|
|
|
|
return -ENOMEM;
|
2010-03-18 03:15:21 +07:00
|
|
|
dev_set_drvdata(&pdev->dev, ssi);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
if (pdata) {
|
|
|
|
ssi->ac97_reset = pdata->ac97_reset;
|
|
|
|
ssi->ac97_warm_reset = pdata->ac97_warm_reset;
|
|
|
|
ssi->flags = pdata->flags;
|
|
|
|
}
|
|
|
|
|
|
|
|
ssi->irq = platform_get_irq(pdev, 0);
|
|
|
|
|
2012-07-28 00:32:10 +07:00
|
|
|
ssi->clk = devm_clk_get(&pdev->dev, NULL);
|
2009-11-25 22:41:04 +07:00
|
|
|
if (IS_ERR(ssi->clk)) {
|
|
|
|
ret = PTR_ERR(ssi->clk);
|
|
|
|
dev_err(&pdev->dev, "Cannot get the clock: %d\n",
|
|
|
|
ret);
|
|
|
|
goto failed_clk;
|
|
|
|
}
|
2013-12-05 05:27:44 +07:00
|
|
|
ret = clk_prepare_enable(ssi->clk);
|
|
|
|
if (ret)
|
|
|
|
goto failed_clk;
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 17:09:26 +07:00
|
|
|
ssi->base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(ssi->base)) {
|
|
|
|
ret = PTR_ERR(ssi->base);
|
2012-07-28 00:32:10 +07:00
|
|
|
goto failed_register;
|
2009-11-25 22:41:04 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ssi->flags & IMX_SSI_USE_AC97) {
|
|
|
|
if (ac97_ssi) {
|
2012-08-01 00:34:07 +07:00
|
|
|
dev_err(&pdev->dev, "AC'97 SSI already registered\n");
|
2009-11-25 22:41:04 +07:00
|
|
|
ret = -EBUSY;
|
2012-07-28 00:32:10 +07:00
|
|
|
goto failed_register;
|
2009-11-25 22:41:04 +07:00
|
|
|
}
|
|
|
|
ac97_ssi = ssi;
|
|
|
|
setup_channel_to_ac97(ssi);
|
2010-03-18 03:15:21 +07:00
|
|
|
dai = &imx_ac97_dai;
|
2009-11-25 22:41:04 +07:00
|
|
|
} else
|
2010-03-18 03:15:21 +07:00
|
|
|
dai = &imx_ssi_dai;
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
writel(0x0, ssi->base + SSI_SIER);
|
|
|
|
|
2013-04-03 16:06:04 +07:00
|
|
|
ssi->dma_params_rx.addr = res->start + SSI_SRX0;
|
|
|
|
ssi->dma_params_tx.addr = res->start + SSI_STX0;
|
2009-11-25 22:41:04 +07:00
|
|
|
|
2013-04-03 16:06:04 +07:00
|
|
|
ssi->dma_params_tx.maxburst = 6;
|
|
|
|
ssi->dma_params_rx.maxburst = 4;
|
|
|
|
|
|
|
|
ssi->dma_params_tx.filter_data = &ssi->filter_data_tx;
|
|
|
|
ssi->dma_params_rx.filter_data = &ssi->filter_data_rx;
|
2011-03-01 21:02:06 +07:00
|
|
|
|
2009-11-25 22:41:04 +07:00
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
|
2013-03-22 20:12:12 +07:00
|
|
|
if (res) {
|
2013-04-03 16:06:04 +07:00
|
|
|
imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
|
2013-07-25 16:41:41 +07:00
|
|
|
IMX_DMATYPE_SSI);
|
2013-03-22 20:12:12 +07:00
|
|
|
}
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
|
2013-03-22 20:12:12 +07:00
|
|
|
if (res) {
|
2013-04-03 16:06:04 +07:00
|
|
|
imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
|
2013-07-25 16:41:41 +07:00
|
|
|
IMX_DMATYPE_SSI);
|
2013-03-22 20:12:12 +07:00
|
|
|
}
|
2009-11-25 22:41:04 +07:00
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
platform_set_drvdata(pdev, ssi);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
2013-06-26 18:45:59 +07:00
|
|
|
ret = snd_soc_set_ac97_ops(&imx_ssi_ac97_ops);
|
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
|
|
|
|
goto failed_register;
|
|
|
|
}
|
|
|
|
|
2013-03-21 17:32:15 +07:00
|
|
|
ret = snd_soc_register_component(&pdev->dev, &imx_component,
|
|
|
|
dai, 1);
|
2009-11-25 22:41:04 +07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "register DAI failed\n");
|
|
|
|
goto failed_register;
|
|
|
|
}
|
|
|
|
|
2013-06-20 20:20:21 +07:00
|
|
|
ssi->fiq_params.irq = ssi->irq;
|
|
|
|
ssi->fiq_params.base = ssi->base;
|
|
|
|
ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
|
|
|
|
ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
|
|
|
|
|
2013-10-01 19:36:10 +07:00
|
|
|
ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
|
|
|
|
ssi->dma_init = imx_pcm_dma_init(pdev);
|
2010-11-04 23:05:42 +07:00
|
|
|
|
2013-10-01 19:36:10 +07:00
|
|
|
if (ssi->fiq_init && ssi->dma_init) {
|
|
|
|
ret = ssi->fiq_init;
|
|
|
|
goto failed_pcm;
|
|
|
|
}
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2013-10-01 19:36:10 +07:00
|
|
|
failed_pcm:
|
2013-03-21 17:32:15 +07:00
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2009-11-25 22:41:04 +07:00
|
|
|
failed_register:
|
2012-05-26 03:27:20 +07:00
|
|
|
clk_disable_unprepare(ssi->clk);
|
2009-11-25 22:41:04 +07:00
|
|
|
failed_clk:
|
2013-06-26 18:45:59 +07:00
|
|
|
snd_soc_set_ac97_ops(NULL);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-07 21:26:16 +07:00
|
|
|
static int imx_ssi_remove(struct platform_device *pdev)
|
2009-11-25 22:41:04 +07:00
|
|
|
{
|
|
|
|
struct imx_ssi *ssi = platform_get_drvdata(pdev);
|
|
|
|
|
2013-10-01 19:36:10 +07:00
|
|
|
if (!ssi->fiq_init)
|
|
|
|
imx_pcm_fiq_exit(pdev);
|
2010-03-18 03:15:21 +07:00
|
|
|
|
2013-03-21 17:32:15 +07:00
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
if (ssi->flags & IMX_SSI_USE_AC97)
|
|
|
|
ac97_ssi = NULL;
|
|
|
|
|
2012-05-26 03:27:20 +07:00
|
|
|
clk_disable_unprepare(ssi->clk);
|
2013-06-26 18:45:59 +07:00
|
|
|
snd_soc_set_ac97_ops(NULL);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver imx_ssi_driver = {
|
|
|
|
.probe = imx_ssi_probe,
|
2012-12-07 21:26:16 +07:00
|
|
|
.remove = imx_ssi_remove,
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
.driver = {
|
2010-10-01 03:46:14 +07:00
|
|
|
.name = "imx-ssi",
|
2009-11-25 22:41:04 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-11-24 14:03:50 +07:00
|
|
|
module_platform_driver(imx_ssi_driver);
|
2009-11-25 22:41:04 +07:00
|
|
|
|
|
|
|
/* Module information */
|
|
|
|
MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
|
|
|
|
MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
|
|
|
|
MODULE_LICENSE("GPL");
|
2011-06-23 03:21:49 +07:00
|
|
|
MODULE_ALIAS("platform:imx-ssi");
|