2013-08-14 16:44:06 +07:00
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/*
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* otg.c - ChipIdea USB IP core OTG driver
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* Author: Peter Chen
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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2014-04-23 14:56:50 +07:00
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* This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
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* are also included.
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2013-08-14 16:44:06 +07:00
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*/
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#include <linux/usb/otg.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/chipidea.h>
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#include "ci.h"
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#include "bits.h"
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#include "otg.h"
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2014-04-23 14:56:44 +07:00
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#include "otg_fsm.h"
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2013-08-14 16:44:06 +07:00
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2014-04-23 14:56:38 +07:00
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/**
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* hw_read_otgsc returns otgsc register bits value.
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* @mask: bitfield mask
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*/
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u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
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{
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return hw_read(ci, OP_OTGSC, mask);
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}
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/**
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* hw_write_otgsc updates target bits of OTGSC register.
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* @mask: bitfield mask
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* @data: to be written
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*/
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void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
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{
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hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
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}
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2013-08-14 16:44:06 +07:00
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/**
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2013-08-14 16:44:10 +07:00
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* ci_otg_role - pick role based on ID pin state
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* @ci: the controller
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*/
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enum ci_role ci_otg_role(struct ci_hdrc *ci)
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{
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2014-04-23 14:56:38 +07:00
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enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
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2013-08-14 16:44:10 +07:00
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? CI_ROLE_GADGET
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: CI_ROLE_HOST;
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return role;
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}
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2013-08-14 16:44:11 +07:00
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void ci_handle_vbus_change(struct ci_hdrc *ci)
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{
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if (!ci->is_otg)
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return;
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2014-04-23 14:56:38 +07:00
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if (hw_read_otgsc(ci, OTGSC_BSV))
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2013-08-14 16:44:11 +07:00
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usb_gadget_vbus_connect(&ci->gadget);
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else
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usb_gadget_vbus_disconnect(&ci->gadget);
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}
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2013-08-14 16:44:12 +07:00
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#define CI_VBUS_STABLE_TIMEOUT_MS 5000
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2013-08-14 16:44:11 +07:00
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static void ci_handle_id_switch(struct ci_hdrc *ci)
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2013-08-14 16:44:10 +07:00
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{
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enum ci_role role = ci_otg_role(ci);
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if (role != ci->role) {
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dev_dbg(ci->dev, "switching from %s to %s\n",
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ci_role(ci)->name, ci->roles[role]->name);
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ci_role_stop(ci);
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2013-08-14 16:44:12 +07:00
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/* wait vbus lower than OTGSC_BSV */
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hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0,
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CI_VBUS_STABLE_TIMEOUT_MS);
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2013-08-14 16:44:10 +07:00
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ci_role_start(ci, role);
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}
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2013-08-14 16:44:11 +07:00
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}
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/**
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* ci_otg_work - perform otg (vbus/id) event handle
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* @work: work struct
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*/
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static void ci_otg_work(struct work_struct *work)
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{
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struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
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2014-04-23 14:56:50 +07:00
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if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) {
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enable_irq(ci->irq);
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return;
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}
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2013-08-14 16:44:11 +07:00
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if (ci->id_event) {
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ci->id_event = false;
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ci_handle_id_switch(ci);
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} else if (ci->b_sess_valid_event) {
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ci->b_sess_valid_event = false;
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ci_handle_vbus_change(ci);
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} else
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dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
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2013-08-14 16:44:10 +07:00
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enable_irq(ci->irq);
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}
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2013-08-14 16:44:11 +07:00
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2013-08-14 16:44:10 +07:00
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/**
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* ci_hdrc_otg_init - initialize otg struct
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2013-08-14 16:44:06 +07:00
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* ci: the controller
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*/
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int ci_hdrc_otg_init(struct ci_hdrc *ci)
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{
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2013-08-14 16:44:11 +07:00
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INIT_WORK(&ci->work, ci_otg_work);
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2013-08-14 16:44:10 +07:00
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ci->wq = create_singlethread_workqueue("ci_otg");
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if (!ci->wq) {
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dev_err(ci->dev, "can't create workqueue\n");
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return -ENODEV;
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}
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2013-08-14 16:44:06 +07:00
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2014-04-23 14:56:44 +07:00
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if (ci_otg_is_fsm_mode(ci))
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return ci_hdrc_otg_fsm_init(ci);
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2013-08-14 16:44:06 +07:00
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return 0;
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}
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2013-08-14 16:44:10 +07:00
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/**
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* ci_hdrc_otg_destroy - destroy otg struct
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* ci: the controller
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*/
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void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
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{
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if (ci->wq) {
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flush_workqueue(ci->wq);
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destroy_workqueue(ci->wq);
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}
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2014-04-23 14:56:38 +07:00
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/* Disable all OTG irq and clear status */
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hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
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OTGSC_INT_STATUS_BITS);
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2014-04-23 14:56:51 +07:00
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if (ci_otg_is_fsm_mode(ci))
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ci_hdrc_otg_fsm_remove(ci);
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2013-08-14 16:44:10 +07:00
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}
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