linux_dsm_epyc7002/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Ming Huang <ming.huang@mediatek.com>
 *	   Sean Wang <sean.wang@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/input/input.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "MediaTek MT7622 RFB1 board";
	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";

	chosen {
		bootargs = "console=ttyS0,115200n1";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys-polled";
		poll-interval = <100>;

		factory {
			label = "factory";
			linux,code = <BTN_0>;
			gpios = <&pio 0 0>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 0>;
		};
	};

	memory {
		reg = <0 0x40000000 0 0x3F000000>;
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";

	pcie@0,0 {
		status = "okay";
	};
};

&pio {
	/* eMMC is shared pin with parallel NAND */
	emmc_pins_default: emmc-pins-default {
		mux {
			function = "emmc", "emmc_rst";
			groups = "emmc";
		};
	};

	emmc_pins_uhs: emmc-pins-uhs {
		mux {
			function = "emmc";
			groups = "emmc";
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	i2c1_pins: i2c1-pins {
		mux {
			function = "i2c";
			groups =  "i2c1_0";
		};
	};

	i2c2_pins: i2c2-pins {
		mux {
			function = "i2c";
			groups =  "i2c2_0";
		};
	};

	i2s1_pins: i2s1-pins {
		mux {
			function = "i2s";
			groups =  "i2s_out_bclk_ws_mclk",
				  "i2s1_in_data",
				  "i2s1_out_data";
		};
	};

	irrx_pins: irrx-pins {
		mux {
			function = "ir";
			groups =  "ir_1_rx";
		};
	};

	irtx_pins: irtx-pins {
		mux {
			function = "ir";
			groups =  "ir_1_tx";
		};
	};

	/* Parallel nand is shared pin with eMMC */
	parallel_nand_pins: parallel-nand-pins {
		mux {
			function = "flash";
			groups = "par_nand";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie1_pad_perst",
				 "pcie1_0_waken",
				 "pcie1_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm7_pins: pwm1-2-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch7_2";
		};
	};

	wled_pins: wled-pins {
		mux {
			function = "led";
			groups = "wled";
		};
	};

	sd0_pins_default: sd0-pins-default {
		mux {
			function = "sd";
			groups = "sd_0";
		};
	};

	sd0_pins_uhs: sd0-pins-uhs {
		mux {
			function = "sd";
			groups = "sd_0";
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	spic0_pins: spic0-pins {
		mux {
			function = "spi";
			groups = "spic0_0";
		};
	};

	spic1_pins: spic1-pins {
		mux {
			function = "spi";
			groups = "spic1_0";
		};
	};

	/* SPI-NOR is shared pin with serial NAND */
	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	/* serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2_1_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&bch {
	status = "disabled";
};

&btif {
	status = "okay";
};

&cir {
	pinctrl-names = "default";
	pinctrl-0 = <&irrx_pins>;
	status = "okay";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&eth_pins>;
	status = "okay";

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-handle = <&phy5>;
	};

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		phy5: ethernet-phy@5 {
			reg = <5>;
			phy-mode = "sgmii";
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&nandc {
	pinctrl-names = "default";
	pinctrl-0 = <&parallel_nand_pins>;
	status = "disabled";
};

&nor_flash {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_nor_pins>;
	status = "disabled";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;

	status = "okay";
};

&sata {
	status = "okay";
};

&sata_phy {
	status = "okay";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic1_pins>;
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};