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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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*/
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#ifndef __ASM_IP32_INTS_H
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#define __ASM_IP32_INTS_H
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/*
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* This list reflects the assignment of interrupt numbers to
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* interrupting events. Order is fairly irrelevant to handling
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* priority. This differs from irix.
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*/
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/* CPU */
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#define IP32_R4K_TIMER_IRQ 0
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/* MACE */
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#define MACE_VID_IN1_IRQ 1
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#define MACE_VID_IN2_IRQ 2
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#define MACE_VID_OUT_IRQ 3
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#define MACE_ETHERNET_IRQ 4
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/* SUPERIO, MISC, and AUDIO are MACEISA */
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#define MACE_PCI_BRIDGE_IRQ 8
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/* MACEPCI */
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#define MACEPCI_SCSI0_IRQ 9
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#define MACEPCI_SCSI1_IRQ 10
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#define MACEPCI_SLOT0_IRQ 11
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#define MACEPCI_SLOT1_IRQ 12
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#define MACEPCI_SLOT2_IRQ 13
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#define MACEPCI_SHARED0_IRQ 14
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#define MACEPCI_SHARED1_IRQ 15
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#define MACEPCI_SHARED2_IRQ 16
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/* CRIME */
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#define CRIME_GBE0_IRQ 17
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#define CRIME_GBE1_IRQ 18
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#define CRIME_GBE2_IRQ 19
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#define CRIME_GBE3_IRQ 20
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#define CRIME_CPUERR_IRQ 21
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#define CRIME_MEMERR_IRQ 22
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#define CRIME_RE_EMPTY_E_IRQ 23
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#define CRIME_RE_FULL_E_IRQ 24
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#define CRIME_RE_IDLE_E_IRQ 25
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#define CRIME_RE_EMPTY_L_IRQ 26
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#define CRIME_RE_FULL_L_IRQ 27
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#define CRIME_RE_IDLE_L_IRQ 28
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#define CRIME_SOFT0_IRQ 29
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#define CRIME_SOFT1_IRQ 30
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#define CRIME_SOFT2_IRQ 31
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#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
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#define CRIME_VICE_IRQ 32
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/* MACEISA */
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#define MACEISA_AUDIO_SW_IRQ 33
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#define MACEISA_AUDIO_SC_IRQ 34
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#define MACEISA_AUDIO1_DMAT_IRQ 35
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#define MACEISA_AUDIO1_OF_IRQ 36
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#define MACEISA_AUDIO2_DMAT_IRQ 37
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#define MACEISA_AUDIO2_MERR_IRQ 38
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#define MACEISA_AUDIO3_DMAT_IRQ 39
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#define MACEISA_AUDIO3_MERR_IRQ 40
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#define MACEISA_RTC_IRQ 41
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#define MACEISA_KEYB_IRQ 42
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/* MACEISA_KEYB_POLL is not an IRQ */
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#define MACEISA_MOUSE_IRQ 44
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/* MACEISA_MOUSE_POLL is not an IRQ */
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#define MACEISA_TIMER0_IRQ 46
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#define MACEISA_TIMER1_IRQ 47
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#define MACEISA_TIMER2_IRQ 48
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#define MACEISA_PARALLEL_IRQ 49
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#define MACEISA_PAR_CTXA_IRQ 50
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#define MACEISA_PAR_CTXB_IRQ 51
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#define MACEISA_PAR_MERR_IRQ 52
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#define MACEISA_SERIAL1_IRQ 53
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#define MACEISA_SERIAL1_TDMAT_IRQ 54
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#define MACEISA_SERIAL1_TDMAPR_IRQ 55
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#define MACEISA_SERIAL1_TDMAME_IRQ 56
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#define MACEISA_SERIAL1_RDMAT_IRQ 57
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#define MACEISA_SERIAL1_RDMAOR_IRQ 58
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#define MACEISA_SERIAL2_IRQ 59
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#define MACEISA_SERIAL2_TDMAT_IRQ 60
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#define MACEISA_SERIAL2_TDMAPR_IRQ 61
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#define MACEISA_SERIAL2_TDMAME_IRQ 62
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#define MACEISA_SERIAL2_RDMAT_IRQ 63
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#define MACEISA_SERIAL2_RDMAOR_IRQ 64
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#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
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#endif /* __ASM_IP32_INTS_H */
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