2019-05-27 13:55:01 +07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
2017-12-01 13:05:41 +07:00
|
|
|
/*
|
|
|
|
|
* Copyright (C) Icenowy Zheng <icenowy@aosc.io>
|
|
|
|
|
*
|
|
|
|
|
* Based on sun4i_layer.h, which is:
|
|
|
|
|
* Copyright (C) 2015 Free Electrons
|
|
|
|
|
* Copyright (C) 2015 NextThing Co
|
|
|
|
|
*
|
|
|
|
|
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <drm/drm_atomic.h>
|
|
|
|
|
#include <drm/drm_atomic_helper.h>
|
|
|
|
|
#include <drm/drm_crtc.h>
|
|
|
|
|
#include <drm/drm_fb_cma_helper.h>
|
2019-07-16 13:42:06 +07:00
|
|
|
#include <drm/drm_fourcc.h>
|
2017-12-01 13:05:41 +07:00
|
|
|
#include <drm/drm_gem_cma_helper.h>
|
2018-11-22 08:44:17 +07:00
|
|
|
#include <drm/drm_gem_framebuffer_helper.h>
|
2017-12-01 13:05:41 +07:00
|
|
|
#include <drm/drm_plane_helper.h>
|
2019-01-18 04:03:34 +07:00
|
|
|
#include <drm/drm_probe_helper.h>
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
#include "sun8i_ui_layer.h"
|
|
|
|
|
#include "sun8i_mixer.h"
|
2017-12-01 13:05:44 +07:00
|
|
|
#include "sun8i_ui_scaler.h"
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
|
2018-07-17 19:25:22 +07:00
|
|
|
int overlay, bool enable, unsigned int zpos,
|
|
|
|
|
unsigned int old_zpos)
|
2017-12-01 13:05:41 +07:00
|
|
|
{
|
2018-11-05 01:26:46 +07:00
|
|
|
u32 val, bld_base, ch_base;
|
|
|
|
|
|
|
|
|
|
bld_base = sun8i_blender_base(mixer);
|
|
|
|
|
ch_base = sun8i_channel_base(mixer, channel);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
|
|
|
|
|
enable ? "En" : "Dis", channel, overlay);
|
|
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
|
val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
|
|
|
|
|
else
|
|
|
|
|
val = 0;
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
|
2017-12-01 13:05:41 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
|
|
|
|
|
|
2018-07-17 19:25:22 +07:00
|
|
|
if (!enable || zpos != old_zpos) {
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
2018-07-17 19:25:22 +07:00
|
|
|
SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
|
|
|
|
|
0);
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
2018-07-17 19:25:22 +07:00
|
|
|
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
|
|
|
|
|
0);
|
|
|
|
|
}
|
|
|
|
|
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
if (enable) {
|
|
|
|
|
val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
|
|
|
|
|
val, val);
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
|
|
|
|
|
val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_ROUTE(bld_base),
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
|
|
|
|
|
val);
|
|
|
|
|
}
|
2017-12-01 13:05:41 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
int overlay, struct drm_plane *plane,
|
|
|
|
|
unsigned int zpos)
|
2017-12-01 13:05:41 +07:00
|
|
|
{
|
|
|
|
|
struct drm_plane_state *state = plane->state;
|
2017-12-01 13:05:44 +07:00
|
|
|
u32 src_w, src_h, dst_w, dst_h;
|
2018-11-05 01:26:46 +07:00
|
|
|
u32 bld_base, ch_base;
|
2017-12-01 13:05:44 +07:00
|
|
|
u32 outsize, insize;
|
|
|
|
|
u32 hphase, vphase;
|
2017-12-01 13:05:41 +07:00
|
|
|
|
2017-12-01 13:05:44 +07:00
|
|
|
DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
|
|
|
|
|
channel, overlay);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
2018-11-05 01:26:46 +07:00
|
|
|
bld_base = sun8i_blender_base(mixer);
|
|
|
|
|
ch_base = sun8i_channel_base(mixer, channel);
|
|
|
|
|
|
2017-12-01 13:05:44 +07:00
|
|
|
src_w = drm_rect_width(&state->src) >> 16;
|
|
|
|
|
src_h = drm_rect_height(&state->src) >> 16;
|
|
|
|
|
dst_w = drm_rect_width(&state->dst);
|
|
|
|
|
dst_h = drm_rect_height(&state->dst);
|
|
|
|
|
|
|
|
|
|
hphase = state->src.x1 & 0xffff;
|
|
|
|
|
vphase = state->src.y1 & 0xffff;
|
|
|
|
|
|
|
|
|
|
insize = SUN8I_MIXER_SIZE(src_w, src_h);
|
|
|
|
|
outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
|
|
|
|
|
bool interlaced = false;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
|
2017-12-01 13:05:44 +07:00
|
|
|
dst_w, dst_h);
|
2017-12-01 13:05:41 +07:00
|
|
|
regmap_write(mixer->engine.regs,
|
|
|
|
|
SUN8I_MIXER_GLOBAL_SIZE,
|
2017-12-01 13:05:44 +07:00
|
|
|
outsize);
|
2018-11-05 01:26:46 +07:00
|
|
|
regmap_write(mixer->engine.regs,
|
|
|
|
|
SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
if (state->crtc)
|
|
|
|
|
interlaced = state->crtc->state->adjusted_mode.flags
|
|
|
|
|
& DRM_MODE_FLAG_INTERLACE;
|
|
|
|
|
|
|
|
|
|
if (interlaced)
|
|
|
|
|
val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
|
|
|
|
|
else
|
|
|
|
|
val = 0;
|
|
|
|
|
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_OUTCTL(bld_base),
|
2017-12-01 13:05:41 +07:00
|
|
|
SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
|
|
|
|
|
val);
|
|
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
|
|
|
|
|
interlaced ? "on" : "off");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set height and width */
|
2017-12-01 13:05:44 +07:00
|
|
|
DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
|
|
|
|
|
state->src.x1 >> 16, state->src.y1 >> 16);
|
|
|
|
|
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
|
2017-12-01 13:05:41 +07:00
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
|
2017-12-01 13:05:44 +07:00
|
|
|
insize);
|
2017-12-01 13:05:41 +07:00
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
|
2017-12-01 13:05:44 +07:00
|
|
|
insize);
|
|
|
|
|
|
|
|
|
|
if (insize != outsize || hphase || vphase) {
|
|
|
|
|
u32 hscale, vscale;
|
|
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("HW scaling is enabled\n");
|
|
|
|
|
|
|
|
|
|
hscale = state->src_w / state->crtc_w;
|
|
|
|
|
vscale = state->src_h / state->crtc_h;
|
|
|
|
|
|
|
|
|
|
sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
|
|
|
|
|
dst_h, hscale, vscale, hphase, vphase);
|
|
|
|
|
sun8i_ui_scaler_enable(mixer, channel, true);
|
|
|
|
|
} else {
|
|
|
|
|
DRM_DEBUG_DRIVER("HW scaling is not needed\n");
|
|
|
|
|
sun8i_ui_scaler_enable(mixer, channel, false);
|
|
|
|
|
}
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
/* Set base coordinates */
|
2017-12-01 13:05:44 +07:00
|
|
|
DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
|
2017-12-01 13:05:41 +07:00
|
|
|
state->dst.x1, state->dst.y1);
|
2017-12-01 13:05:44 +07:00
|
|
|
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
|
2017-12-01 13:05:41 +07:00
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
|
2017-12-01 13:05:41 +07:00
|
|
|
SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
|
|
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
|
2017-12-01 13:05:44 +07:00
|
|
|
outsize);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
|
|
|
|
|
int overlay, struct drm_plane *plane)
|
|
|
|
|
{
|
|
|
|
|
struct drm_plane_state *state = plane->state;
|
|
|
|
|
const struct de2_fmt_info *fmt_info;
|
2018-11-05 01:26:46 +07:00
|
|
|
u32 val, ch_base;
|
|
|
|
|
|
|
|
|
|
ch_base = sun8i_channel_base(mixer, channel);
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
fmt_info = sun8i_mixer_format_info(state->fb->format->format);
|
2017-12-01 13:05:47 +07:00
|
|
|
if (!fmt_info || !fmt_info->rgb) {
|
2017-12-01 13:05:41 +07:00
|
|
|
DRM_DEBUG_DRIVER("Invalid format\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
|
|
|
|
|
regmap_update_bits(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
|
2017-12-01 13:05:41 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
|
|
|
|
|
int overlay, struct drm_plane *plane)
|
|
|
|
|
{
|
|
|
|
|
struct drm_plane_state *state = plane->state;
|
|
|
|
|
struct drm_framebuffer *fb = state->fb;
|
|
|
|
|
struct drm_gem_cma_object *gem;
|
|
|
|
|
dma_addr_t paddr;
|
2018-11-05 01:26:46 +07:00
|
|
|
u32 ch_base;
|
2017-12-01 13:05:41 +07:00
|
|
|
int bpp;
|
|
|
|
|
|
2018-11-05 01:26:46 +07:00
|
|
|
ch_base = sun8i_channel_base(mixer, channel);
|
|
|
|
|
|
2017-12-01 13:05:41 +07:00
|
|
|
/* Get the physical address of the buffer in memory */
|
|
|
|
|
gem = drm_fb_cma_get_gem_obj(fb, 0);
|
|
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
|
|
|
|
|
|
|
|
|
|
/* Compute the start of the displayed memory */
|
|
|
|
|
bpp = fb->format->cpp[0];
|
|
|
|
|
paddr = gem->paddr + fb->offsets[0];
|
|
|
|
|
|
|
|
|
|
/* Fixup framebuffer address for src coordinates */
|
|
|
|
|
paddr += (state->src.x1 >> 16) * bpp;
|
|
|
|
|
paddr += (state->src.y1 >> 16) * fb->pitches[0];
|
|
|
|
|
|
|
|
|
|
/* Set the line width */
|
|
|
|
|
DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
|
|
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
|
2017-12-01 13:05:41 +07:00
|
|
|
fb->pitches[0]);
|
|
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
|
|
|
|
|
|
|
|
|
|
regmap_write(mixer->engine.regs,
|
2018-11-05 01:26:46 +07:00
|
|
|
SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
|
2017-12-01 13:05:41 +07:00
|
|
|
lower_32_bits(paddr));
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
|
|
|
|
|
struct drm_plane_state *state)
|
|
|
|
|
{
|
2017-12-01 13:05:44 +07:00
|
|
|
struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
|
2017-12-01 13:05:41 +07:00
|
|
|
struct drm_crtc *crtc = state->crtc;
|
|
|
|
|
struct drm_crtc_state *crtc_state;
|
2017-12-01 13:05:44 +07:00
|
|
|
int min_scale, max_scale;
|
2017-12-01 13:05:41 +07:00
|
|
|
|
|
|
|
|
if (!crtc)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
|
|
|
|
|
if (WARN_ON(!crtc_state))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2017-12-01 13:05:44 +07:00
|
|
|
min_scale = DRM_PLANE_HELPER_NO_SCALING;
|
|
|
|
|
max_scale = DRM_PLANE_HELPER_NO_SCALING;
|
|
|
|
|
|
|
|
|
|
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
|
|
|
|
|
min_scale = SUN8I_UI_SCALER_SCALE_MIN;
|
|
|
|
|
max_scale = SUN8I_UI_SCALER_SCALE_MAX;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-24 00:08:57 +07:00
|
|
|
return drm_atomic_helper_check_plane_state(state, crtc_state,
|
2017-12-01 13:05:44 +07:00
|
|
|
min_scale, max_scale,
|
2017-12-01 13:05:41 +07:00
|
|
|
true, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
|
|
|
|
|
struct drm_plane_state *old_state)
|
|
|
|
|
{
|
|
|
|
|
struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
|
2018-07-17 19:25:22 +07:00
|
|
|
unsigned int old_zpos = old_state->normalized_zpos;
|
2017-12-01 13:05:41 +07:00
|
|
|
struct sun8i_mixer *mixer = layer->mixer;
|
|
|
|
|
|
2018-07-17 19:25:22 +07:00
|
|
|
sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
|
|
|
|
|
old_zpos);
|
2017-12-01 13:05:41 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
|
|
|
|
|
struct drm_plane_state *old_state)
|
|
|
|
|
{
|
|
|
|
|
struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
unsigned int zpos = plane->state->normalized_zpos;
|
2018-07-17 19:25:22 +07:00
|
|
|
unsigned int old_zpos = old_state->normalized_zpos;
|
2017-12-01 13:05:41 +07:00
|
|
|
struct sun8i_mixer *mixer = layer->mixer;
|
|
|
|
|
|
|
|
|
|
if (!plane->state->visible) {
|
|
|
|
|
sun8i_ui_layer_enable(mixer, layer->channel,
|
2018-07-17 19:25:22 +07:00
|
|
|
layer->overlay, false, 0, old_zpos);
|
2017-12-01 13:05:41 +07:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
sun8i_ui_layer_update_coord(mixer, layer->channel,
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
layer->overlay, plane, zpos);
|
2017-12-01 13:05:41 +07:00
|
|
|
sun8i_ui_layer_update_formats(mixer, layer->channel,
|
|
|
|
|
layer->overlay, plane);
|
|
|
|
|
sun8i_ui_layer_update_buffer(mixer, layer->channel,
|
|
|
|
|
layer->overlay, plane);
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
|
2018-07-17 19:25:22 +07:00
|
|
|
true, zpos, old_zpos);
|
2017-12-01 13:05:41 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
|
2018-11-22 08:44:17 +07:00
|
|
|
.prepare_fb = drm_gem_fb_prepare_fb,
|
2017-12-01 13:05:41 +07:00
|
|
|
.atomic_check = sun8i_ui_layer_atomic_check,
|
|
|
|
|
.atomic_disable = sun8i_ui_layer_atomic_disable,
|
|
|
|
|
.atomic_update = sun8i_ui_layer_atomic_update,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct drm_plane_funcs sun8i_ui_layer_funcs = {
|
|
|
|
|
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
|
|
|
|
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
|
|
|
|
.destroy = drm_plane_cleanup,
|
|
|
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
|
|
|
|
.reset = drm_atomic_helper_plane_reset,
|
|
|
|
|
.update_plane = drm_atomic_helper_update_plane,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const u32 sun8i_ui_layer_formats[] = {
|
|
|
|
|
DRM_FORMAT_ABGR1555,
|
|
|
|
|
DRM_FORMAT_ABGR4444,
|
|
|
|
|
DRM_FORMAT_ABGR8888,
|
|
|
|
|
DRM_FORMAT_ARGB1555,
|
|
|
|
|
DRM_FORMAT_ARGB4444,
|
|
|
|
|
DRM_FORMAT_ARGB8888,
|
|
|
|
|
DRM_FORMAT_BGR565,
|
|
|
|
|
DRM_FORMAT_BGR888,
|
|
|
|
|
DRM_FORMAT_BGRA5551,
|
|
|
|
|
DRM_FORMAT_BGRA4444,
|
|
|
|
|
DRM_FORMAT_BGRA8888,
|
|
|
|
|
DRM_FORMAT_BGRX8888,
|
|
|
|
|
DRM_FORMAT_RGB565,
|
|
|
|
|
DRM_FORMAT_RGB888,
|
|
|
|
|
DRM_FORMAT_RGBA4444,
|
|
|
|
|
DRM_FORMAT_RGBA5551,
|
|
|
|
|
DRM_FORMAT_RGBA8888,
|
|
|
|
|
DRM_FORMAT_RGBX8888,
|
|
|
|
|
DRM_FORMAT_XBGR8888,
|
|
|
|
|
DRM_FORMAT_XRGB8888,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
|
|
|
|
|
struct sun8i_mixer *mixer,
|
|
|
|
|
int index)
|
|
|
|
|
{
|
|
|
|
|
enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
|
int channel = mixer->cfg->vi_num + index;
|
|
|
|
|
struct sun8i_ui_layer *layer;
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
unsigned int plane_cnt;
|
2017-12-01 13:05:41 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
|
|
|
|
|
if (!layer)
|
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
|
|
if (index == 0)
|
|
|
|
|
type = DRM_PLANE_TYPE_PRIMARY;
|
|
|
|
|
|
|
|
|
|
/* possible crtcs are set later */
|
|
|
|
|
ret = drm_universal_plane_init(drm, &layer->plane, 0,
|
|
|
|
|
&sun8i_ui_layer_funcs,
|
|
|
|
|
sun8i_ui_layer_formats,
|
|
|
|
|
ARRAY_SIZE(sun8i_ui_layer_formats),
|
|
|
|
|
NULL, type, NULL);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(drm->dev, "Couldn't initialize layer\n");
|
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
|
}
|
|
|
|
|
|
drm/sun4i: Implement zpos for DE2
Initial implementation of DE2 planes only supported fixed zpos.
Expand implementation with configurable zpos property.
Implementation background:
Channel in DE2 driver represents one DRM plane, whereas pipe is just
mapped channel to known Z position. Pipe 0 will always be at the bottom,
pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped
at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear
on top.
Before this commit, channel id was used for addressing channel related
registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_)
and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally,
register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels
to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so
on. Consequence of all that was fixed Z order of planes.
With this commit, pipe registers are using zpos property as index and
channel related registers still use channel id as index. Pipe mapping
register is now set dynamically too and pipe enable register is rebuild
every time to make sure only active pipes are enabled.
Testing was done to confirm that there is no issues if bottom plane
contains pixels with alpha value < 0xff and if it doesn't whole screen.
Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
|
|
|
plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
|
|
|
|
|
|
|
|
|
|
ret = drm_plane_create_zpos_property(&layer->plane, channel,
|
|
|
|
|
0, plane_cnt - 1);
|
2017-12-01 13:05:41 +07:00
|
|
|
if (ret) {
|
|
|
|
|
dev_err(drm->dev, "Couldn't add zpos property\n");
|
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
|
|
|
|
|
layer->mixer = mixer;
|
|
|
|
|
layer->channel = channel;
|
|
|
|
|
layer->overlay = 0;
|
|
|
|
|
|
|
|
|
|
return layer;
|
|
|
|
|
}
|