AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
9e98c678c2
linux_dsm_epyc7002/drivers/clk/actions/owl-pll.h

111 lines
2.7 KiB
C
Raw Normal View History

clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
// SPDX-License-Identifier: GPL-2.0+
//
// OWL pll clock driver
//
// Copyright (c) 2014 Actions Semi Inc.
// Author: David Liu <liuwei@actions-semi.com>
//
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
#ifndef _OWL_PLL_H_
#define _OWL_PLL_H_
#include "owl-common.h"
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
#define OWL_PLL_DEF_DELAY 50
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
/* last entry should have rate = 0 */
struct clk_pll_table {
unsigned int val;
unsigned long rate;
};
struct owl_pll_hw {
u32 reg;
u32 bfreq;
u8 bit_idx;
u8 shift;
u8 width;
u8 min_mul;
u8 max_mul;
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
u8 delay;
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
const struct clk_pll_table *table;
};
struct owl_pll {
struct owl_pll_hw pll_hw;
struct owl_clk_common common;
};
#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
_width, _min_mul, _max_mul, _delay, _table) \
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
{ \
.reg = _reg, \
.bfreq = _bfreq, \
.bit_idx = _bit_idx, \
.shift = _shift, \
.width = _width, \
.min_mul = _min_mul, \
.max_mul = _max_mul, \
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
.delay = _delay, \
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
.table = _table, \
}
#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
_shift, _width, _min_mul, _max_mul, _table, _flags) \
struct owl_pll _struct = { \
.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
_width, _min_mul, _max_mul, \
OWL_PLL_DEF_DELAY, _table), \
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
.common = { \
.regmap = NULL, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&owl_pll_ops, \
_flags), \
}, \
}
#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
_shift, _width, _min_mul, _max_mul, _table, _flags) \
struct owl_pll _struct = { \
.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
clk: actions: Add configurable PLL delay S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-15 10:33:35 +07:00
_width, _min_mul, _max_mul, \
OWL_PLL_DEF_DELAY, _table), \
.common = { \
.regmap = NULL, \
.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
&owl_pll_ops, \
_flags), \
}, \
}
#define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
_shift, _width, _min_mul, _max_mul, _delay, _table, \
_flags) \
struct owl_pll _struct = { \
.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
_width, _min_mul, _max_mul, \
_delay, _table), \
clk: actions: Add pll clock support Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-27 00:39:04 +07:00
.common = { \
.regmap = NULL, \
.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
&owl_pll_ops, \
_flags), \
}, \
}
#define mul_mask(m) ((1 << ((m)->width)) - 1)
static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
{
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
return container_of(common, struct owl_pll, common);
}
extern const struct clk_ops owl_pll_ops;
#endif /* _OWL_PLL_H_ */
Reference in New Issue Copy Permalink