License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2005-04-26 21:21:02 +07:00
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#include <linux/init.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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2005-09-10 02:08:59 +07:00
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#include <asm/asm-offsets.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/errno.h>
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2005-04-26 21:21:02 +07:00
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#include <asm/thread_info.h>
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2010-05-22 00:06:42 +07:00
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#include <asm/v7m.h>
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2005-04-17 05:20:36 +07:00
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@ Bad Abort numbers
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@ -----------------
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@
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#define BAD_PREFETCH 0
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#define BAD_DATA 1
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#define BAD_ADDREXCPTN 2
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#define BAD_IRQ 3
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#define BAD_UNDEFINSTR 4
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@
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2005-04-26 21:18:59 +07:00
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@ Most of the stack format comes from struct pt_regs, but with
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@ the addition of 8 bytes for storing syscall args 5 and 6.
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2006-01-14 23:18:08 +07:00
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@ This _must_ remain a multiple of 8 for EABI.
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2005-04-17 05:20:36 +07:00
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@
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#define S_OFF 8
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2005-04-26 21:18:59 +07:00
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/*
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* The SWI code relies on the fact that R0 is at the bottom of the stack
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* (due to slow/fast restore user regs).
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*/
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#if S_R0 != 0
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#error "Please fix"
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#endif
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2005-04-26 21:21:02 +07:00
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.macro zero_fp
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#ifdef CONFIG_FRAME_POINTER
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mov fp, #0
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#endif
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.endm
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2005-04-17 05:20:36 +07:00
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#ifdef CONFIG_ALIGNMENT_TRAP
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2014-08-28 19:08:14 +07:00
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#define ATRAP(x...) x
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#else
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#define ATRAP(x...)
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#endif
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.macro alignment_trap, rtmp1, rtmp2, label
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#ifdef CONFIG_ALIGNMENT_TRAP
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mrc p15, 0, \rtmp2, c1, c0, 0
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ldr \rtmp1, \label
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ldr \rtmp1, [\rtmp1]
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teq \rtmp1, \rtmp2
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mcrne p15, 0, \rtmp1, c1, c0, 0
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2005-04-17 05:20:36 +07:00
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#endif
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.endm
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2010-05-22 00:06:42 +07:00
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#ifdef CONFIG_CPU_V7M
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/*
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* ARMv7-M exception entry/exit macros.
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*
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* xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
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* automatically saved on the current stack (32 words) before
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* switching to the exception stack (SP_main).
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*
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* If exception is taken while in user mode, SP_main is
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* empty. Otherwise, SP_main is aligned to 64 bit automatically
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* (CCR.STKALIGN set).
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*
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* Linux assumes that the interrupts are disabled when entering an
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* exception handler and it may BUG if this is not the case. Interrupts
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* are disabled during entry and reenabled in the exit macro.
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*
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* v7m_exception_slow_exit is used when returning from SVC or PendSV.
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* When returning to kernel mode, we don't return from exception.
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*/
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.macro v7m_exception_entry
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@ determine the location of the registers saved by the core during
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@ exception entry. Depending on the mode the cpu was in when the
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@ exception happend that is either on the main or the process stack.
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@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
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@ was used.
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tst lr, #EXC_RET_STACK_MASK
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mrsne r12, psp
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moveq r12, sp
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@ we cannot rely on r0-r3 and r12 matching the value saved in the
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@ exception frame because of tail-chaining. So these have to be
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@ reloaded.
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ldmia r12!, {r0-r3}
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@ Linux expects to have irqs off. Do it here before taking stack space
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cpsid i
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2016-05-10 22:34:27 +07:00
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sub sp, #PT_REGS_SIZE-S_IP
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2010-05-22 00:06:42 +07:00
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stmdb sp!, {r0-r11}
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@ load saved r12, lr, return address and xPSR.
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@ r0-r7 are used for signals and never touched from now on. Clobbering
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@ r8-r12 is OK.
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mov r9, r12
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ldmia r9!, {r8, r10-r12}
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@ calculate the original stack pointer value.
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@ r9 currently points to the memory location just above the auto saved
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@ xPSR.
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@ The cpu might automatically 8-byte align the stack. Bit 9
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@ of the saved xPSR specifies if stack aligning took place. In this case
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@ another 32-bit value is included in the stack.
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tst r12, V7M_xPSR_FRAMEPTRALIGN
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addne r9, r9, #4
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@ store saved r12 using str to have a register to hold the base for stm
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str r8, [sp, #S_IP]
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add r8, sp, #S_SP
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@ store r13-r15, xPSR
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stmia r8!, {r9-r12}
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@ store old_r0
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str r0, [r8]
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.endm
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/*
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* PENDSV and SVCALL are configured to have the same exception
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* priorities. As a kernel thread runs at SVCALL execution priority it
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* can never be preempted and so we will never have to return to a
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* kernel thread here.
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*/
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.macro v7m_exception_slow_exit ret_r0
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cpsid i
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ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
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@ read original r12, sp, lr, pc and xPSR
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add r12, sp, #S_IP
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ldmia r12, {r1-r5}
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@ an exception frame is always 8-byte aligned. To tell the hardware if
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@ the sp to be restored is aligned or not set bit 9 of the saved xPSR
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@ accordingly.
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tst r2, #4
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subne r2, r2, #4
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orrne r5, V7M_xPSR_FRAMEPTRALIGN
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biceq r5, V7M_xPSR_FRAMEPTRALIGN
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2014-05-24 23:38:01 +07:00
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@ ensure bit 0 is cleared in the PC, otherwise behaviour is
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@ unpredictable
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bic r4, #1
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2010-05-22 00:06:42 +07:00
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@ write basic exception frame
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stmdb r2!, {r1, r3-r5}
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ldmia sp, {r1, r3-r5}
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.if \ret_r0
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stmdb r2!, {r0, r3-r5}
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.else
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stmdb r2!, {r1, r3-r5}
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.endif
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@ restore process sp
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msr psp, r2
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@ restore original r4-r11
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ldmia sp!, {r0-r11}
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@ restore main sp
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2016-05-10 22:34:27 +07:00
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add sp, sp, #PT_REGS_SIZE-S_IP
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2010-05-22 00:06:42 +07:00
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cpsie i
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bx lr
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.endm
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#endif /* CONFIG_CPU_V7M */
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2009-07-24 18:32:54 +07:00
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@
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@ Store/load the USER SP and LR registers by switching to the SYS
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@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
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@ available. Should only be called from SVC mode
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@
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.macro store_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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str sp, [\rd, #\offset] @ save sp_usr
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str lr, [\rd, #\offset + 4] @ save lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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.macro load_user_sp_lr, rd, rtemp, offset = 0
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mrs \rtemp, cpsr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch to the SYS mode
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ldr sp, [\rd, #\offset] @ load sp_usr
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ldr lr, [\rd, #\offset + 4] @ load lr_usr
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eor \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
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msr cpsr_c, \rtemp @ switch back to the SVC mode
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.endm
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2015-08-27 02:07:25 +07:00
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2013-03-28 19:57:40 +07:00
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.macro svc_exit, rpsr, irq = 0
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.if \irq != 0
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2013-03-28 21:36:05 +07:00
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@ IRQs already off
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2013-03-28 19:57:40 +07:00
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#ifdef CONFIG_TRACE_IRQFLAGS
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@ The parent context IRQs must have been enabled to get here in
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@ the first place, so there's no point checking the PSR I bit.
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bl trace_hardirqs_on
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#endif
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.else
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2013-03-28 21:36:05 +07:00
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@ IRQs off again before pulling preserved data off the stack
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disable_irq_notrace
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2013-03-28 19:57:40 +07:00
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst \rpsr, #PSR_I_BIT
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bleq trace_hardirqs_on
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tst \rpsr, #PSR_I_BIT
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blne trace_hardirqs_off
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#endif
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.endif
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2016-05-13 17:40:20 +07:00
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ldr r1, [sp, #SVC_ADDR_LIMIT]
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2015-08-20 16:32:02 +07:00
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uaccess_restore
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2016-05-13 17:40:20 +07:00
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str r1, [tsk, #TI_ADDR_LIMIT]
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2015-08-27 02:07:25 +07:00
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#ifndef CONFIG_THUMB2_KERNEL
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@ ARM mode SVC restore
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2009-07-24 18:32:54 +07:00
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msr spsr_cxsf, \rpsr
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2014-08-15 18:11:50 +07:00
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
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@ We must avoid clrex due to Cortex-A15 erratum #830321
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sub r0, sp, #4 @ uninhabited address
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strex r1, r2, [r0] @ clear the exclusive monitor
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2009-09-19 05:27:05 +07:00
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#endif
|
2014-08-15 18:11:50 +07:00
|
|
|
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
2015-08-27 02:07:25 +07:00
|
|
|
#else
|
|
|
|
|
@ Thumb mode SVC restore
|
|
|
|
|
ldr lr, [sp, #S_SP] @ top of the stack
|
|
|
|
|
ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
|
|
|
|
|
|
|
|
|
|
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
|
|
|
|
strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor
|
|
|
|
|
|
|
|
|
|
stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
|
|
|
|
|
ldmia sp, {r0 - r12}
|
|
|
|
|
mov sp, lr
|
|
|
|
|
ldr lr, [sp], #4
|
|
|
|
|
rfeia sp!
|
|
|
|
|
#endif
|
2009-07-24 18:32:54 +07:00
|
|
|
.endm
|
|
|
|
|
|
2014-09-17 23:12:06 +07:00
|
|
|
@
|
|
|
|
|
@ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
|
|
|
|
|
@
|
|
|
|
|
@ This macro acts in a similar manner to svc_exit but switches to FIQ
|
|
|
|
|
@ mode to restore the final part of the register state.
|
|
|
|
|
@
|
|
|
|
|
@ We cannot use the normal svc_exit procedure because that would
|
|
|
|
|
@ clobber spsr_svc (FIQ could be delivered during the first few
|
|
|
|
|
@ instructions of vector_swi meaning its contents have not been
|
|
|
|
|
@ saved anywhere).
|
|
|
|
|
@
|
|
|
|
|
@ Note that, unlike svc_exit, this macro also does not allow a caller
|
|
|
|
|
@ supplied rpsr. This is because the FIQ exceptions are not re-entrant
|
|
|
|
|
@ and the handlers cannot call into the scheduler (meaning the value
|
|
|
|
|
@ on the stack remains correct).
|
|
|
|
|
@
|
|
|
|
|
.macro svc_exit_via_fiq
|
2016-05-13 17:40:20 +07:00
|
|
|
ldr r1, [sp, #SVC_ADDR_LIMIT]
|
2015-08-20 16:32:02 +07:00
|
|
|
uaccess_restore
|
2016-05-13 17:40:20 +07:00
|
|
|
str r1, [tsk, #TI_ADDR_LIMIT]
|
2015-08-27 02:07:25 +07:00
|
|
|
#ifndef CONFIG_THUMB2_KERNEL
|
|
|
|
|
@ ARM mode restore
|
2014-09-17 23:12:06 +07:00
|
|
|
mov r0, sp
|
|
|
|
|
ldmib r0, {r1 - r14} @ abort is deadly from here onward (it will
|
|
|
|
|
@ clobber state restored below)
|
|
|
|
|
msr cpsr_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
|
|
|
|
|
add r8, r0, #S_PC
|
|
|
|
|
ldr r9, [r0, #S_PSR]
|
|
|
|
|
msr spsr_cxsf, r9
|
|
|
|
|
ldr r0, [r0, #S_R0]
|
|
|
|
|
ldmia r8, {pc}^
|
2015-08-27 02:07:25 +07:00
|
|
|
#else
|
|
|
|
|
@ Thumb mode restore
|
|
|
|
|
add r0, sp, #S_R2
|
|
|
|
|
ldr lr, [sp, #S_LR]
|
|
|
|
|
ldr sp, [sp, #S_SP] @ abort is deadly from here onward (it will
|
|
|
|
|
@ clobber state restored below)
|
|
|
|
|
ldmia r0, {r2 - r12}
|
|
|
|
|
mov r1, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
|
|
|
|
|
msr cpsr_c, r1
|
|
|
|
|
sub r0, #S_R2
|
|
|
|
|
add r8, r0, #S_PC
|
|
|
|
|
ldmia r0, {r0 - r1}
|
|
|
|
|
rfeia r8
|
|
|
|
|
#endif
|
2014-09-17 23:12:06 +07:00
|
|
|
.endm
|
|
|
|
|
|
2015-08-27 02:07:25 +07:00
|
|
|
|
2009-07-24 18:32:54 +07:00
|
|
|
.macro restore_user_regs, fast = 0, offset = 0
|
2015-08-20 16:32:02 +07:00
|
|
|
uaccess_enable r1, isb=0
|
2015-08-27 02:07:25 +07:00
|
|
|
#ifndef CONFIG_THUMB2_KERNEL
|
|
|
|
|
@ ARM mode restore
|
2015-01-10 00:30:13 +07:00
|
|
|
mov r2, sp
|
|
|
|
|
ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
|
|
|
|
|
ldr lr, [r2, #\offset + S_PC]! @ get pc
|
2017-11-27 18:22:42 +07:00
|
|
|
tst r1, #PSR_I_BIT | 0x0f
|
2017-11-25 06:49:34 +07:00
|
|
|
bne 1f
|
2009-07-24 18:32:54 +07:00
|
|
|
msr spsr_cxsf, r1 @ save in spsr_svc
|
2014-08-15 18:11:50 +07:00
|
|
|
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
|
|
|
|
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
2015-01-10 00:30:13 +07:00
|
|
|
strex r1, r2, [r2] @ clear the exclusive monitor
|
2009-09-19 05:27:05 +07:00
|
|
|
#endif
|
2009-07-24 18:32:54 +07:00
|
|
|
.if \fast
|
2015-01-10 00:30:13 +07:00
|
|
|
ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
|
2009-07-24 18:32:54 +07:00
|
|
|
.else
|
2015-01-10 00:30:13 +07:00
|
|
|
ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
|
2009-07-24 18:32:54 +07:00
|
|
|
.endif
|
2010-03-15 22:04:14 +07:00
|
|
|
mov r0, r0 @ ARMv5T and earlier require a nop
|
|
|
|
|
@ after ldm {}^
|
2016-05-10 22:34:27 +07:00
|
|
|
add sp, sp, #\offset + PT_REGS_SIZE
|
2009-07-24 18:32:54 +07:00
|
|
|
movs pc, lr @ return & move spsr_svc into cpsr
|
2017-11-25 06:49:34 +07:00
|
|
|
1: bug "Returning to usermode but unexpected PSR bits set?", \@
|
2015-08-27 02:07:25 +07:00
|
|
|
#elif defined(CONFIG_CPU_V7M)
|
|
|
|
|
@ V7M restore.
|
|
|
|
|
@ Note that we don't need to do clrex here as clearing the local
|
|
|
|
|
@ monitor is part of the exception entry and exit sequence.
|
2010-05-22 00:06:42 +07:00
|
|
|
.if \offset
|
|
|
|
|
add sp, #\offset
|
|
|
|
|
.endif
|
|
|
|
|
v7m_exception_slow_exit ret_r0 = \fast
|
2015-08-27 02:07:25 +07:00
|
|
|
#else
|
|
|
|
|
@ Thumb mode restore
|
2009-07-24 18:32:54 +07:00
|
|
|
mov r2, sp
|
|
|
|
|
load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
|
|
|
|
|
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
|
|
|
|
ldr lr, [sp, #\offset + S_PC] @ get pc
|
|
|
|
|
add sp, sp, #\offset + S_SP
|
2017-11-27 18:22:42 +07:00
|
|
|
tst r1, #PSR_I_BIT | 0x0f
|
2017-11-25 06:49:34 +07:00
|
|
|
bne 1f
|
2009-07-24 18:32:54 +07:00
|
|
|
msr spsr_cxsf, r1 @ save in spsr_svc
|
2014-08-15 18:11:50 +07:00
|
|
|
|
|
|
|
|
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
|
|
|
|
strex r1, r2, [sp] @ clear the exclusive monitor
|
|
|
|
|
|
2009-07-24 18:32:54 +07:00
|
|
|
.if \fast
|
|
|
|
|
ldmdb sp, {r1 - r12} @ get calling r1 - r12
|
|
|
|
|
.else
|
|
|
|
|
ldmdb sp, {r0 - r12} @ get calling r0 - r12
|
|
|
|
|
.endif
|
2016-05-10 22:34:27 +07:00
|
|
|
add sp, sp, #PT_REGS_SIZE - S_SP
|
2009-07-24 18:32:54 +07:00
|
|
|
movs pc, lr @ return & move spsr_svc into cpsr
|
2017-11-25 06:49:34 +07:00
|
|
|
1: bug "Returning to usermode but unexpected PSR bits set?", \@
|
2009-07-24 18:32:54 +07:00
|
|
|
#endif /* !CONFIG_THUMB2_KERNEL */
|
2015-08-27 02:07:25 +07:00
|
|
|
.endm
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-03-29 04:54:40 +07:00
|
|
|
/*
|
|
|
|
|
* Context tracking subsystem. Used to instrument transitions
|
|
|
|
|
* between user and kernel mode.
|
|
|
|
|
*/
|
|
|
|
|
.macro ct_user_exit, save = 1
|
|
|
|
|
#ifdef CONFIG_CONTEXT_TRACKING
|
|
|
|
|
.if \save
|
|
|
|
|
stmdb sp!, {r0-r3, ip, lr}
|
2013-09-10 05:54:17 +07:00
|
|
|
bl context_tracking_user_exit
|
2013-03-29 04:54:40 +07:00
|
|
|
ldmia sp!, {r0-r3, ip, lr}
|
|
|
|
|
.else
|
2013-09-10 05:54:17 +07:00
|
|
|
bl context_tracking_user_exit
|
2013-03-29 04:54:40 +07:00
|
|
|
.endif
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro ct_user_enter, save = 1
|
|
|
|
|
#ifdef CONFIG_CONTEXT_TRACKING
|
|
|
|
|
.if \save
|
|
|
|
|
stmdb sp!, {r0-r3, ip, lr}
|
2013-09-10 05:54:17 +07:00
|
|
|
bl context_tracking_user_enter
|
2013-03-29 04:54:40 +07:00
|
|
|
ldmia sp!, {r0-r3, ip, lr}
|
|
|
|
|
.else
|
2013-09-10 05:54:17 +07:00
|
|
|
bl context_tracking_user_enter
|
2013-03-29 04:54:40 +07:00
|
|
|
.endif
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2018-05-11 17:16:22 +07:00
|
|
|
.macro invoke_syscall, table, nr, tmp, ret, reload=0
|
|
|
|
|
#ifdef CONFIG_CPU_SPECTRE
|
|
|
|
|
mov \tmp, \nr
|
|
|
|
|
cmp \tmp, #NR_syscalls @ check upper syscall limit
|
|
|
|
|
movcs \tmp, #0
|
|
|
|
|
csdb
|
|
|
|
|
badr lr, \ret @ return address
|
|
|
|
|
.if \reload
|
|
|
|
|
add r1, sp, #S_R0 + S_OFF @ pointer to regs
|
|
|
|
|
ldmccia r1, {r0 - r6} @ reload r0-r6
|
|
|
|
|
stmccia sp, {r4, r5} @ update stack arguments
|
|
|
|
|
.endif
|
|
|
|
|
ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine
|
|
|
|
|
#else
|
|
|
|
|
cmp \nr, #NR_syscalls @ check upper syscall limit
|
|
|
|
|
badr lr, \ret @ return address
|
|
|
|
|
.if \reload
|
|
|
|
|
add r1, sp, #S_R0 + S_OFF @ pointer to regs
|
|
|
|
|
ldmccia r1, {r0 - r6} @ reload r0-r6
|
|
|
|
|
stmccia sp, {r4, r5} @ update stack arguments
|
|
|
|
|
.endif
|
|
|
|
|
ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/*
|
|
|
|
|
* These are the registers used in the syscall handler, and allow us to
|
|
|
|
|
* have in theory up to 7 arguments to a function - r0 to r6.
|
|
|
|
|
*
|
|
|
|
|
* r7 is reserved for the system call number for thumb mode.
|
|
|
|
|
*
|
|
|
|
|
* Note that tbl == why is intentional.
|
|
|
|
|
*
|
|
|
|
|
* We must set at least "tsk" and "why" when calling ret_with_reschedule.
|
|
|
|
|
*/
|
|
|
|
|
scno .req r7 @ syscall number
|
|
|
|
|
tbl .req r8 @ syscall table pointer
|
|
|
|
|
why .req r8 @ Linux syscall (!= 0)
|
|
|
|
|
tsk .req r9 @ current thread_info
|