2018-02-08 02:47:58 +07:00
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// SPDX-License-Identifier: GPL-2.0+
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2005-04-17 05:20:36 +07:00
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/*
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* Support for common PCI multi-I/O cards (which is most of them)
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*
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* Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
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*
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* Multi-function PCI cards are supposed to present separate logical
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* devices on the bus. A common thing to do seems to be to just use
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* one logical device with lots of base address registers for both
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* parallel ports and serial ports. This driver is for dealing with
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* that.
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*/
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2009-04-07 21:30:57 +07:00
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#include <linux/interrupt.h>
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2018-02-08 02:47:57 +07:00
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#include <linux/module.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/parport.h>
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#include <linux/parport_pc.h>
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2018-02-08 02:47:57 +07:00
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/8250_pci.h>
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enum parport_pc_pci_cards {
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titan_110l = 0,
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titan_210l,
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netmos_9xx5_combo,
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2005-06-23 14:09:55 +07:00
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netmos_9855,
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parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 06:58:53 +07:00
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netmos_9855_2p,
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Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
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netmos_9900,
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netmos_9900_2p,
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netmos_99xx_1p,
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2005-04-17 05:20:36 +07:00
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avlab_1s1p,
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avlab_1s2p,
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avlab_2s1p,
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siig_1s1p_10x,
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siig_2s1p_10x,
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siig_2p1s_20x,
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siig_1s1p_20x,
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siig_2s1p_20x,
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2011-05-30 02:08:04 +07:00
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timedia_4078a,
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timedia_4079h,
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timedia_4085h,
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timedia_4088a,
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timedia_4089a,
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timedia_4095a,
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timedia_4096a,
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timedia_4078u,
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timedia_4079a,
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timedia_4085u,
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timedia_4079r,
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timedia_4079s,
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timedia_4079d,
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timedia_4079e,
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timedia_4079f,
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timedia_9079a,
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timedia_9079b,
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timedia_9079c,
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2014-05-25 01:24:51 +07:00
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wch_ch353_1s1p,
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2012-09-04 21:56:12 +07:00
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wch_ch353_2s1p,
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2018-05-26 20:39:45 +07:00
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wch_ch382_0s1p,
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2014-11-06 18:36:31 +07:00
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wch_ch382_2s1p,
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2018-02-08 02:47:51 +07:00
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brainboxes_5s1p,
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2019-08-10 02:01:30 +07:00
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sunix_4008a,
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sunix_5069a,
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sunix_5079a,
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sunix_5099a,
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2005-04-17 05:20:36 +07:00
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};
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/* each element directly indexed from enum list, above */
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struct parport_pc_pci {
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int numports;
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struct { /* BAR (base address registers) numbers in the config
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space header */
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int lo;
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int hi; /* -1 if not there, >6 for offset-method (max
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BAR is 6) */
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} addr[4];
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/* If set, this is called immediately after pci_enable_device.
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* If it returns non-zero, no probing will take place and the
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* ports will not be used. */
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int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
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int autoirq, int autodma);
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/* If set, this is called after probing for ports. If 'failed'
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* is non-zero we couldn't use any of the ports. */
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void (*postinit_hook) (struct pci_dev *pdev,
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struct parport_pc_pci *card, int failed);
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};
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2012-12-22 04:23:14 +07:00
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static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
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int autoirq, int autodma)
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2005-04-17 05:20:36 +07:00
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{
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2009-02-12 04:04:40 +07:00
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/* the rule described below doesn't hold for this device */
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if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
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dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
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dev->subsystem_device == 0x0299)
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return -ENODEV;
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Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
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if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
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par->numports = 1;
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} else {
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/*
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* Netmos uses the subdevice ID to indicate the number of parallel
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* and serial ports. The form is 0x00PS, where <P> is the number of
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* parallel ports and <S> is the number of serial ports.
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*/
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par->numports = (dev->subsystem_device & 0xf0) >> 4;
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if (par->numports > ARRAY_SIZE(par->addr))
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par->numports = ARRAY_SIZE(par->addr);
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}
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2005-04-17 05:20:36 +07:00
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return 0;
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}
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2012-12-22 04:23:14 +07:00
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static struct parport_pc_pci cards[] = {
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2005-04-17 05:20:36 +07:00
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/* titan_110l */ { 1, { { 3, -1 }, } },
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/* titan_210l */ { 1, { { 3, -1 }, } },
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/* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
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parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 06:58:53 +07:00
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/* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
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/* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
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Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
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/* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
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/* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
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/* netmos_99xx_1p */ {1, { { 0, 1 }, } },
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2005-04-17 05:20:36 +07:00
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/* avlab_1s1p */ { 1, { { 1, 2}, } },
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/* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
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/* avlab_2s1p */ { 1, { { 2, 3}, } },
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/* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
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/* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
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/* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
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/* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
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/* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
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2011-05-30 02:08:04 +07:00
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/* timedia_4078a */ { 1, { { 2, -1 }, } },
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/* timedia_4079h */ { 1, { { 2, 3 }, } },
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/* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
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/* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
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/* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
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/* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
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/* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
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/* timedia_4078u */ { 1, { { 2, -1 }, } },
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/* timedia_4079a */ { 1, { { 2, 3 }, } },
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/* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
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/* timedia_4079r */ { 1, { { 2, 3 }, } },
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/* timedia_4079s */ { 1, { { 2, 3 }, } },
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/* timedia_4079d */ { 1, { { 2, 3 }, } },
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/* timedia_4079e */ { 1, { { 2, 3 }, } },
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/* timedia_4079f */ { 1, { { 2, 3 }, } },
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/* timedia_9079a */ { 1, { { 2, 3 }, } },
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/* timedia_9079b */ { 1, { { 2, 3 }, } },
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/* timedia_9079c */ { 1, { { 2, 3 }, } },
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2014-05-25 01:24:51 +07:00
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/* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
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2012-09-04 21:56:12 +07:00
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/* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
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2018-05-26 20:39:45 +07:00
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/* wch_ch382_0s1p*/ { 1, { { 2, -1}, } },
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2014-11-06 18:36:31 +07:00
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/* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
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2018-02-08 02:47:51 +07:00
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/* brainboxes_5s1p */ { 1, { { 3, -1 }, } },
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2019-08-10 02:01:30 +07:00
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/* sunix_4008a */ { 1, { { 1, 2 }, } },
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/* sunix_5069a */ { 1, { { 1, 2 }, } },
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/* sunix_5079a */ { 1, { { 1, 2 }, } },
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/* sunix_5099a */ { 1, { { 1, 2 }, } },
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2005-04-17 05:20:36 +07:00
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};
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static struct pci_device_id parport_serial_pci_tbl[] = {
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/* PCI cards */
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
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{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
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{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
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{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
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{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
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parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 06:58:53 +07:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
|
|
|
0x1000, 0x0020, 0, 0, netmos_9855_2p },
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
|
|
|
0x1000, 0x0022, 0, 0, netmos_9855_2p },
|
2005-04-17 05:20:36 +07:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
2005-06-23 14:09:55 +07:00
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
0xA000, 0x3011, 0, 0, netmos_9900 },
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
0xA000, 0x3012, 0, 0, netmos_9900 },
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
0xA000, 0x3020, 0, 0, netmos_9900_2p },
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
|
|
|
|
0xA000, 0x2000, 0, 0, netmos_99xx_1p },
|
2005-04-17 05:20:36 +07:00
|
|
|
/* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
|
2006-03-21 03:08:22 +07:00
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2110,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2111,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2112,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2140,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2141,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2142,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2160,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2161,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2162,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
2005-04-17 05:20:36 +07:00
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
2011-05-30 02:08:04 +07:00
|
|
|
/* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
|
2013-01-28 15:49:20 +07:00
|
|
|
|
2012-09-04 21:56:12 +07:00
|
|
|
/* WCH CARDS */
|
2014-05-25 01:24:51 +07:00
|
|
|
{ 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
|
2012-09-04 21:56:12 +07:00
|
|
|
{ 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
|
2018-05-26 20:39:45 +07:00
|
|
|
{ 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p},
|
2014-11-06 18:36:31 +07:00
|
|
|
{ 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
|
2013-01-28 15:49:20 +07:00
|
|
|
|
2018-02-08 02:47:51 +07:00
|
|
|
/* BrainBoxes PX272/PX306 MIO card */
|
|
|
|
{ PCI_VENDOR_ID_INTASHIELD, 0x4100,
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_5s1p },
|
|
|
|
|
2019-08-10 02:01:30 +07:00
|
|
|
/* Sunix boards */
|
2013-01-28 15:49:20 +07:00
|
|
|
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
|
2019-08-10 02:01:30 +07:00
|
|
|
0x0100, 0, 0, sunix_4008a },
|
|
|
|
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
|
|
|
|
0x0101, 0, 0, sunix_5069a },
|
|
|
|
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
|
|
|
|
0x0102, 0, 0, sunix_5079a },
|
|
|
|
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
|
|
|
|
0x0104, 0, 0, sunix_5099a },
|
2013-01-28 15:49:20 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
{ 0, } /* terminate list */
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
|
|
|
|
|
2005-07-27 17:41:18 +07:00
|
|
|
/*
|
|
|
|
* This table describes the serial "geometry" of these boards. Any
|
|
|
|
* quirks for these can be found in drivers/serial/8250_pci.c
|
|
|
|
*
|
|
|
|
* Cards not tested are marked n/t
|
|
|
|
* If you have one of these cards and it works for you, please tell me..
|
|
|
|
*/
|
2012-12-22 04:23:14 +07:00
|
|
|
static struct pciserial_board pci_parport_serial_boards[] = {
|
2005-07-27 17:41:18 +07:00
|
|
|
[titan_110l] = {
|
|
|
|
.flags = FL_BASE1 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[titan_210l] = {
|
|
|
|
.flags = FL_BASE1 | FL_BASE_BARS,
|
|
|
|
.num_ports = 2,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[netmos_9xx5_combo] = {
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[netmos_9855] = {
|
parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 06:58:53 +07:00
|
|
|
.flags = FL_BASE2 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[netmos_9855_2p] = {
|
2008-02-06 16:37:44 +07:00
|
|
|
.flags = FL_BASE4 | FL_BASE_BARS,
|
2005-07-27 17:41:18 +07:00
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
|
|
|
[netmos_9900] = { /* n/t */
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[netmos_9900_2p] = { /* parallel only */ /* n/t */
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 0,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[netmos_99xx_1p] = { /* parallel only */ /* n/t */
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 0,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2005-07-27 17:41:18 +07:00
|
|
|
[avlab_1s1p] = { /* n/t */
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[avlab_1s2p] = { /* n/t */
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[avlab_2s1p] = { /* n/t */
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
.num_ports = 2,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[siig_1s1p_10x] = {
|
|
|
|
.flags = FL_BASE2,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 460800,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[siig_2s1p_10x] = {
|
|
|
|
.flags = FL_BASE2,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[siig_2p1s_20x] = {
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[siig_1s1p_20x] = {
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[siig_2s1p_20x] = {
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2011-05-30 02:08:04 +07:00
|
|
|
[timedia_4078a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079h] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4085h] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4088a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4089a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4095a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4096a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4078u] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4085u] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079r] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079s] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079d] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079e] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_4079f] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_9079a] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_9079b] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
|
|
|
[timedia_9079c] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2014-05-25 01:24:51 +07:00
|
|
|
[wch_ch353_1s1p] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2012-09-04 21:56:12 +07:00
|
|
|
[wch_ch353_2s1p] = {
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
.num_ports = 2,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2018-05-26 20:39:45 +07:00
|
|
|
[wch_ch382_0s1p] = {
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 0,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2014-11-06 18:36:31 +07:00
|
|
|
[wch_ch382_2s1p] = {
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
.num_ports = 2,
|
|
|
|
.base_baud = 115200,
|
|
|
|
.uart_offset = 8,
|
|
|
|
.first_offset = 0xC0,
|
|
|
|
},
|
2018-02-08 02:47:51 +07:00
|
|
|
[brainboxes_5s1p] = {
|
|
|
|
.flags = FL_BASE2,
|
|
|
|
.num_ports = 5,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 8,
|
|
|
|
},
|
2019-08-10 02:01:30 +07:00
|
|
|
[sunix_4008a] = {
|
|
|
|
.num_ports = 0,
|
|
|
|
},
|
|
|
|
[sunix_5069a] = {
|
|
|
|
.num_ports = 1,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 0x8,
|
|
|
|
},
|
|
|
|
[sunix_5079a] = {
|
2013-01-28 15:49:20 +07:00
|
|
|
.num_ports = 2,
|
2019-08-10 02:01:30 +07:00
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 0x8,
|
|
|
|
},
|
|
|
|
[sunix_5099a] = {
|
|
|
|
.num_ports = 4,
|
|
|
|
.base_baud = 921600,
|
|
|
|
.uart_offset = 0x8,
|
2013-01-28 15:49:20 +07:00
|
|
|
},
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct parport_serial_private {
|
2005-07-27 17:41:18 +07:00
|
|
|
struct serial_private *serial;
|
2005-04-17 05:20:36 +07:00
|
|
|
int num_par;
|
|
|
|
struct parport *port[PARPORT_MAX];
|
|
|
|
struct parport_pc_pci par;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Register the serial port(s) of a PCI card. */
|
2012-12-22 04:23:14 +07:00
|
|
|
static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
2005-07-27 17:41:18 +07:00
|
|
|
struct pciserial_board *board;
|
|
|
|
struct serial_private *serial;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2005-07-27 17:41:18 +07:00
|
|
|
board = &pci_parport_serial_boards[id->driver_data];
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-06 02:00:37 +07:00
|
|
|
if (board->num_ports == 0)
|
|
|
|
return 0;
|
|
|
|
|
2005-07-27 17:41:18 +07:00
|
|
|
serial = pciserial_init_ports(dev, board);
|
|
|
|
if (IS_ERR(serial))
|
|
|
|
return PTR_ERR(serial);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2005-07-27 17:41:18 +07:00
|
|
|
priv->serial = serial;
|
|
|
|
return 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Register the parallel port(s) of a PCI card. */
|
2012-12-22 04:23:14 +07:00
|
|
|
static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct parport_pc_pci *card;
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
2006-03-05 07:31:22 +07:00
|
|
|
int n, success = 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
priv->par = cards[id->driver_data];
|
|
|
|
card = &priv->par;
|
|
|
|
if (card->preinit_hook &&
|
|
|
|
card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
for (n = 0; n < card->numports; n++) {
|
|
|
|
struct parport *port;
|
|
|
|
int lo = card->addr[n].lo;
|
|
|
|
int hi = card->addr[n].hi;
|
|
|
|
unsigned long io_lo, io_hi;
|
2009-04-07 21:30:57 +07:00
|
|
|
int irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
if (priv->num_par == ARRAY_SIZE (priv->port)) {
|
2018-02-08 02:47:55 +07:00
|
|
|
dev_warn(&dev->dev,
|
|
|
|
"only %zu parallel ports supported (%d reported)\n",
|
|
|
|
ARRAY_SIZE(priv->port), card->numports);
|
2005-04-17 05:20:36 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
io_lo = pci_resource_start (dev, lo);
|
|
|
|
io_hi = 0;
|
|
|
|
if ((hi >= 0) && (hi <= 6))
|
|
|
|
io_hi = pci_resource_start (dev, hi);
|
|
|
|
else if (hi > 6)
|
|
|
|
io_lo += hi; /* Reinterpret the meaning of
|
|
|
|
"hi" as an offset (see SYBA
|
|
|
|
def.) */
|
|
|
|
/* TODO: test if sharing interrupts works */
|
2009-04-07 21:30:57 +07:00
|
|
|
irq = dev->irq;
|
|
|
|
if (irq == IRQ_NONE) {
|
|
|
|
dev_dbg(&dev->dev,
|
2018-02-08 02:47:55 +07:00
|
|
|
"PCI parallel port detected: I/O at %#lx(%#lx)\n",
|
2009-04-07 21:30:57 +07:00
|
|
|
io_lo, io_hi);
|
|
|
|
irq = PARPORT_IRQ_NONE;
|
|
|
|
} else {
|
|
|
|
dev_dbg(&dev->dev,
|
2018-02-08 02:47:55 +07:00
|
|
|
"PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
|
2009-04-07 21:30:57 +07:00
|
|
|
io_lo, io_hi, irq);
|
|
|
|
}
|
|
|
|
port = parport_pc_probe_port (io_lo, io_hi, irq,
|
|
|
|
PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (port) {
|
|
|
|
priv->port[priv->num_par++] = port;
|
|
|
|
success = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (card->postinit_hook)
|
|
|
|
card->postinit_hook (dev, card, !success);
|
|
|
|
|
2006-03-05 07:31:22 +07:00
|
|
|
return 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2012-12-22 04:23:14 +07:00
|
|
|
static int parport_serial_pci_probe(struct pci_dev *dev,
|
|
|
|
const struct pci_device_id *id)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct parport_serial_private *priv;
|
|
|
|
int err;
|
|
|
|
|
2018-02-08 02:47:53 +07:00
|
|
|
priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
2018-02-08 02:47:53 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
pci_set_drvdata (dev, priv);
|
|
|
|
|
2018-02-08 02:47:53 +07:00
|
|
|
err = pcim_enable_device(dev);
|
|
|
|
if (err)
|
2005-04-17 05:20:36 +07:00
|
|
|
return err;
|
|
|
|
|
2018-02-08 02:47:54 +07:00
|
|
|
err = parport_register(dev, id);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2018-02-08 02:47:54 +07:00
|
|
|
err = serial_register(dev, id);
|
|
|
|
if (err) {
|
2005-04-17 05:20:36 +07:00
|
|
|
int i;
|
|
|
|
for (i = 0; i < priv->num_par; i++)
|
|
|
|
parport_pc_unregister_port (priv->port[i]);
|
2018-02-08 02:47:54 +07:00
|
|
|
return err;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-22 04:23:14 +07:00
|
|
|
static void parport_serial_pci_remove(struct pci_dev *dev)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
// Serial ports
|
2005-07-27 17:41:18 +07:00
|
|
|
if (priv->serial)
|
|
|
|
pciserial_remove_ports(priv->serial);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
// Parallel ports
|
|
|
|
for (i = 0; i < priv->num_par; i++)
|
|
|
|
parport_pc_unregister_port (priv->port[i]);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-08 02:47:52 +07:00
|
|
|
static int __maybe_unused parport_serial_pci_suspend(struct device *dev)
|
2005-07-27 17:41:18 +07:00
|
|
|
{
|
2019-08-02 02:14:08 +07:00
|
|
|
struct parport_serial_private *priv = dev_get_drvdata(dev);
|
2005-07-27 17:41:18 +07:00
|
|
|
|
|
|
|
if (priv->serial)
|
|
|
|
pciserial_suspend_ports(priv->serial);
|
|
|
|
|
|
|
|
/* FIXME: What about parport? */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-08 02:47:52 +07:00
|
|
|
static int __maybe_unused parport_serial_pci_resume(struct device *dev)
|
2005-07-27 17:41:18 +07:00
|
|
|
{
|
2019-08-02 02:14:08 +07:00
|
|
|
struct parport_serial_private *priv = dev_get_drvdata(dev);
|
2005-07-27 17:41:18 +07:00
|
|
|
|
|
|
|
if (priv->serial)
|
|
|
|
pciserial_resume_ports(priv->serial);
|
|
|
|
|
|
|
|
/* FIXME: What about parport? */
|
|
|
|
return 0;
|
|
|
|
}
|
2018-02-08 02:47:52 +07:00
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(parport_serial_pm_ops,
|
|
|
|
parport_serial_pci_suspend, parport_serial_pci_resume);
|
2005-07-27 17:41:18 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
static struct pci_driver parport_serial_pci_driver = {
|
|
|
|
.name = "parport_serial",
|
|
|
|
.id_table = parport_serial_pci_tbl,
|
|
|
|
.probe = parport_serial_pci_probe,
|
2012-12-22 04:23:14 +07:00
|
|
|
.remove = parport_serial_pci_remove,
|
2018-02-08 02:47:52 +07:00
|
|
|
.driver = {
|
|
|
|
.pm = &parport_serial_pm_ops,
|
|
|
|
},
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
2018-02-08 02:47:56 +07:00
|
|
|
module_pci_driver(parport_serial_pci_driver);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
|
|
|
|
MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
|
|
|
|
MODULE_LICENSE("GPL");
|