2019-01-20 15:25:53 +07:00
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// SPDX-License-Identifier: GPL-2.0
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// ff-protocol-latter - a part of driver for RME Fireface series
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//
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// Copyright (c) 2019 Takashi Sakamoto
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//
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// Licensed under the terms of the GNU General Public License, version 2.
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#include <linux/delay.h>
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#include "ff.h"
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#define LATTER_STF 0xffff00000004
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#define LATTER_ISOC_CHANNELS 0xffff00000008
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#define LATTER_ISOC_START 0xffff0000000c
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#define LATTER_FETCH_MODE 0xffff00000010
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#define LATTER_SYNC_STATUS 0x0000801c0000
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static int parse_clock_bits(u32 data, unsigned int *rate,
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enum snd_ff_clock_src *src)
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{
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static const struct {
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unsigned int rate;
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u32 flag;
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} *rate_entry, rate_entries[] = {
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{ 32000, 0x00000000, },
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{ 44100, 0x01000000, },
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{ 48000, 0x02000000, },
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{ 64000, 0x04000000, },
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{ 88200, 0x05000000, },
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{ 96000, 0x06000000, },
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{ 128000, 0x08000000, },
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{ 176400, 0x09000000, },
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{ 192000, 0x0a000000, },
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};
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static const struct {
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enum snd_ff_clock_src src;
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u32 flag;
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} *clk_entry, clk_entries[] = {
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{ SND_FF_CLOCK_SRC_SPDIF, 0x00000200, },
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{ SND_FF_CLOCK_SRC_ADAT1, 0x00000400, },
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{ SND_FF_CLOCK_SRC_WORD, 0x00000600, },
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{ SND_FF_CLOCK_SRC_INTERNAL, 0x00000e00, },
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
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rate_entry = rate_entries + i;
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if ((data & 0x0f000000) == rate_entry->flag) {
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*rate = rate_entry->rate;
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break;
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}
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}
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if (i == ARRAY_SIZE(rate_entries))
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return -EIO;
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for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
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clk_entry = clk_entries + i;
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if ((data & 0x000e00) == clk_entry->flag) {
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*src = clk_entry->src;
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_entries))
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return -EIO;
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return 0;
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}
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static int latter_get_clock(struct snd_ff *ff, unsigned int *rate,
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enum snd_ff_clock_src *src)
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{
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__le32 reg;
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u32 data;
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int err;
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err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
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LATTER_SYNC_STATUS, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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data = le32_to_cpu(reg);
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return parse_clock_bits(data, rate, src);
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}
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static int latter_switch_fetching_mode(struct snd_ff *ff, bool enable)
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{
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u32 data;
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__le32 reg;
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if (enable)
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data = 0x00000000;
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else
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data = 0xffffffff;
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reg = cpu_to_le32(data);
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return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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LATTER_FETCH_MODE, ®, sizeof(reg), 0);
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}
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static int keep_resources(struct snd_ff *ff, unsigned int rate)
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{
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enum snd_ff_stream_mode mode;
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int i;
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int err;
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// Check whether the given value is supported or not.
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for (i = 0; i < CIP_SFC_COUNT; i++) {
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if (amdtp_rate_table[i] == rate)
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break;
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}
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if (i >= CIP_SFC_COUNT)
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return -EINVAL;
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err = snd_ff_stream_get_multiplier_mode(i, &mode);
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if (err < 0)
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return err;
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/* Keep resources for in-stream. */
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ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
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err = fw_iso_resources_allocate(&ff->tx_resources,
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amdtp_stream_get_max_payload(&ff->tx_stream),
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fw_parent_device(ff->unit)->max_speed);
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if (err < 0)
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return err;
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/* Keep resources for out-stream. */
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ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
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err = fw_iso_resources_allocate(&ff->rx_resources,
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amdtp_stream_get_max_payload(&ff->rx_stream),
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fw_parent_device(ff->unit)->max_speed);
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if (err < 0)
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fw_iso_resources_free(&ff->tx_resources);
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return err;
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}
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static int latter_begin_session(struct snd_ff *ff, unsigned int rate)
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{
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static const struct {
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unsigned int stf;
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unsigned int code;
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unsigned int flag;
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} *entry, rate_table[] = {
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{ 32000, 0x00, 0x92, },
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{ 44100, 0x02, 0x92, },
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{ 48000, 0x04, 0x92, },
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{ 64000, 0x08, 0x8e, },
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{ 88200, 0x0a, 0x8e, },
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{ 96000, 0x0c, 0x8e, },
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{ 128000, 0x10, 0x8c, },
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{ 176400, 0x12, 0x8c, },
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{ 192000, 0x14, 0x8c, },
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};
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u32 data;
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__le32 reg;
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unsigned int count;
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int i;
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int err;
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for (i = 0; i < ARRAY_SIZE(rate_table); ++i) {
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entry = rate_table + i;
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if (entry->stf == rate)
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break;
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}
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if (i == ARRAY_SIZE(rate_table))
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return -EINVAL;
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reg = cpu_to_le32(entry->code);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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LATTER_STF, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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// Confirm to shift transmission clock.
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count = 0;
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while (count++ < 10) {
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unsigned int curr_rate;
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enum snd_ff_clock_src src;
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err = latter_get_clock(ff, &curr_rate, &src);
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if (err < 0)
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return err;
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if (curr_rate == rate)
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break;
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}
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if (count == 10)
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return -ETIMEDOUT;
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err = keep_resources(ff, rate);
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if (err < 0)
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return err;
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data = (ff->tx_resources.channel << 8) | ff->rx_resources.channel;
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reg = cpu_to_le32(data);
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err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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LATTER_ISOC_CHANNELS, ®, sizeof(reg), 0);
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if (err < 0)
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return err;
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// Always use the maximum number of data channels in data block of
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// packet.
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reg = cpu_to_le32(entry->flag);
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return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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LATTER_ISOC_START, ®, sizeof(reg), 0);
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}
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static void latter_finish_session(struct snd_ff *ff)
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{
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__le32 reg;
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reg = cpu_to_le32(0x00000000);
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snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
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LATTER_ISOC_START, ®, sizeof(reg), 0);
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}
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static void latter_dump_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
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{
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static const struct {
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char *const label;
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u32 locked_mask;
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u32 synced_mask;
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} *clk_entry, clk_entries[] = {
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{ "S/PDIF", 0x00000001, 0x00000010, },
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{ "ADAT", 0x00000002, 0x00000020, },
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{ "WDClk", 0x00000004, 0x00000040, },
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};
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__le32 reg;
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u32 data;
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unsigned int rate;
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enum snd_ff_clock_src src;
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const char *label;
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int i;
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int err;
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err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
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LATTER_SYNC_STATUS, ®, sizeof(reg), 0);
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if (err < 0)
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return;
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data = le32_to_cpu(reg);
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snd_iprintf(buffer, "External source detection:\n");
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for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
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clk_entry = clk_entries + i;
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snd_iprintf(buffer, "%s: ", clk_entry->label);
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if (data & clk_entry->locked_mask) {
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if (data & clk_entry->synced_mask)
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snd_iprintf(buffer, "sync\n");
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else
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snd_iprintf(buffer, "lock\n");
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} else {
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snd_iprintf(buffer, "none\n");
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}
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}
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err = parse_clock_bits(data, &rate, &src);
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if (err < 0)
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return;
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label = snd_ff_proc_get_clk_label(src);
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if (!label)
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return;
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snd_iprintf(buffer, "Referred clock: %s %d\n", label, rate);
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}
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ALSA: fireface: support tx MIDI functionality of Fireface UCX
Fireface UCX transfers asynchronous transactions for MIDI messages.
One transaction includes quadlet data therefore it can transfer 3
message bytes as maximum. Base address of the destination is
configured by two settings; a register for higher 8 byte of the
address, and a bitflag to option register indicates lower 8byte.
The register for higher address is 0x'ffff'0000'0034. Unfortunately,
firmware v24 includes a bug to ignore registered value for the
destination address and transfers to 0x0001xxxxxxxx always. This
driver doesn't work well if the bug exists, therefore users should
install the latest firmware (v27).
The bitflag is a part of value to be written to option register
(0x'ffff'0000'0014).
lower addr: bitflag (little endian)
'0000'0000: 0x00002000
'0000'0080: 0x00004000
'0000'0100: 0x00008000
'0000'0180: 0x00010000
This register includes more options but they are not relevant to
packet streaming or MIDI functionality. This driver don't touch it.
Furthermore, the transaction is sent to address offset incremented
by 4 byte to the offset in previous time. When it reaches base address
plus 0x7c, next offset is the base address.
Content of the transaction includes a prefix byte. Upper 4 bits of
the byte indicates port number, and the rest 4 bits indicate the way
to decode rest of bytes for MIDI message.
Except for system exclusive messages, the rest bits are the same as
status bits of the message without channel bits. For system exclusive
messages, the rest bits are encoded according to included message bytes.
For example:
message: f0 7e 7f 09 01 f7
offset: content (little endian, port 0)
'0000: 0x04f07e7f
'0004: 0x070901f7
message: f0 00 00 66 14 20 00 00 00 f7
offset: content (little endian, port 1)
'0014: 0x14f00000
'0018: 0x14661420
'001c: 0x14000000
'0020: 0x15f70000
message: f0 00 00 66 14 20 00 00 f7
offset: content (little endian, port 0)
'0078: 0x04f00000
'007c: 0x04661420
'0000: 0x070000f7
This commit supports decoding scheme for the above and allows
applications to receive MIDI messages via ALSA rawmidi interface.
The lower 8 bytes of destination address is fixed to 0x'0000'0000,
thus this driver expects userspace applications to configure option
register with bitflag 0x00002000 in advance.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:02 +07:00
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// NOTE: transactions are transferred within 0x00-0x7f in allocated range of
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// address. This seems to be for check of discontinuity in receiver side.
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2019-01-24 16:32:03 +07:00
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//
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// Like Fireface 400, drivers can select one of 4 options for lower 4 bytes of
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// destination address by bit flags in quadlet register (little endian) at
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// 0x'ffff'0000'0014:
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//
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// bit flags: offset of destination address
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// - 0x00002000: 0x'....'....'0000'0000
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// - 0x00004000: 0x'....'....'0000'0080
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// - 0x00008000: 0x'....'....'0000'0100
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// - 0x00010000: 0x'....'....'0000'0180
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//
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// Drivers can suppress the device to transfer asynchronous transactions by
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// clear these bit flags.
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//
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// Actually, the register is write-only and includes the other settings such as
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// input attenuation. This driver allocates for the first option
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// (0x'....'....'0000'0000) and expects userspace application to configure the
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// register for it.
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ALSA: fireface: support tx MIDI functionality of Fireface UCX
Fireface UCX transfers asynchronous transactions for MIDI messages.
One transaction includes quadlet data therefore it can transfer 3
message bytes as maximum. Base address of the destination is
configured by two settings; a register for higher 8 byte of the
address, and a bitflag to option register indicates lower 8byte.
The register for higher address is 0x'ffff'0000'0034. Unfortunately,
firmware v24 includes a bug to ignore registered value for the
destination address and transfers to 0x0001xxxxxxxx always. This
driver doesn't work well if the bug exists, therefore users should
install the latest firmware (v27).
The bitflag is a part of value to be written to option register
(0x'ffff'0000'0014).
lower addr: bitflag (little endian)
'0000'0000: 0x00002000
'0000'0080: 0x00004000
'0000'0100: 0x00008000
'0000'0180: 0x00010000
This register includes more options but they are not relevant to
packet streaming or MIDI functionality. This driver don't touch it.
Furthermore, the transaction is sent to address offset incremented
by 4 byte to the offset in previous time. When it reaches base address
plus 0x7c, next offset is the base address.
Content of the transaction includes a prefix byte. Upper 4 bits of
the byte indicates port number, and the rest 4 bits indicate the way
to decode rest of bytes for MIDI message.
Except for system exclusive messages, the rest bits are the same as
status bits of the message without channel bits. For system exclusive
messages, the rest bits are encoded according to included message bytes.
For example:
message: f0 7e 7f 09 01 f7
offset: content (little endian, port 0)
'0000: 0x04f07e7f
'0004: 0x070901f7
message: f0 00 00 66 14 20 00 00 00 f7
offset: content (little endian, port 1)
'0014: 0x14f00000
'0018: 0x14661420
'001c: 0x14000000
'0020: 0x15f70000
message: f0 00 00 66 14 20 00 00 f7
offset: content (little endian, port 0)
'0078: 0x04f00000
'007c: 0x04661420
'0000: 0x070000f7
This commit supports decoding scheme for the above and allows
applications to receive MIDI messages via ALSA rawmidi interface.
The lower 8 bytes of destination address is fixed to 0x'0000'0000,
thus this driver expects userspace applications to configure option
register with bitflag 0x00002000 in advance.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:02 +07:00
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static void latter_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
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__le32 *buf, size_t length)
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{
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u32 data = le32_to_cpu(*buf);
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unsigned int index = (data & 0x000000f0) >> 4;
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u8 byte[3];
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struct snd_rawmidi_substream *substream;
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unsigned int len;
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2019-01-25 19:44:18 +07:00
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if (index >= ff->spec->midi_in_ports)
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ALSA: fireface: support tx MIDI functionality of Fireface UCX
Fireface UCX transfers asynchronous transactions for MIDI messages.
One transaction includes quadlet data therefore it can transfer 3
message bytes as maximum. Base address of the destination is
configured by two settings; a register for higher 8 byte of the
address, and a bitflag to option register indicates lower 8byte.
The register for higher address is 0x'ffff'0000'0034. Unfortunately,
firmware v24 includes a bug to ignore registered value for the
destination address and transfers to 0x0001xxxxxxxx always. This
driver doesn't work well if the bug exists, therefore users should
install the latest firmware (v27).
The bitflag is a part of value to be written to option register
(0x'ffff'0000'0014).
lower addr: bitflag (little endian)
'0000'0000: 0x00002000
'0000'0080: 0x00004000
'0000'0100: 0x00008000
'0000'0180: 0x00010000
This register includes more options but they are not relevant to
packet streaming or MIDI functionality. This driver don't touch it.
Furthermore, the transaction is sent to address offset incremented
by 4 byte to the offset in previous time. When it reaches base address
plus 0x7c, next offset is the base address.
Content of the transaction includes a prefix byte. Upper 4 bits of
the byte indicates port number, and the rest 4 bits indicate the way
to decode rest of bytes for MIDI message.
Except for system exclusive messages, the rest bits are the same as
status bits of the message without channel bits. For system exclusive
messages, the rest bits are encoded according to included message bytes.
For example:
message: f0 7e 7f 09 01 f7
offset: content (little endian, port 0)
'0000: 0x04f07e7f
'0004: 0x070901f7
message: f0 00 00 66 14 20 00 00 00 f7
offset: content (little endian, port 1)
'0014: 0x14f00000
'0018: 0x14661420
'001c: 0x14000000
'0020: 0x15f70000
message: f0 00 00 66 14 20 00 00 f7
offset: content (little endian, port 0)
'0078: 0x04f00000
'007c: 0x04661420
'0000: 0x070000f7
This commit supports decoding scheme for the above and allows
applications to receive MIDI messages via ALSA rawmidi interface.
The lower 8 bytes of destination address is fixed to 0x'0000'0000,
thus this driver expects userspace applications to configure option
register with bitflag 0x00002000 in advance.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:02 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
switch (data & 0x0000000f) {
|
|
|
|
case 0x00000008:
|
|
|
|
case 0x00000009:
|
|
|
|
case 0x0000000a:
|
|
|
|
case 0x0000000b:
|
|
|
|
case 0x0000000e:
|
|
|
|
len = 3;
|
|
|
|
break;
|
|
|
|
case 0x0000000c:
|
|
|
|
case 0x0000000d:
|
|
|
|
len = 2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
len = data & 0x00000003;
|
|
|
|
if (len == 0)
|
|
|
|
len = 3;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
byte[0] = (data & 0x0000ff00) >> 8;
|
|
|
|
byte[1] = (data & 0x00ff0000) >> 16;
|
|
|
|
byte[2] = (data & 0xff000000) >> 24;
|
|
|
|
|
|
|
|
substream = READ_ONCE(ff->tx_midi_substreams[index]);
|
|
|
|
if (substream)
|
|
|
|
snd_rawmidi_receive(substream, byte, len);
|
|
|
|
}
|
|
|
|
|
ALSA: fireface: support rx MIDI functionality for Fireface UCX
In latter model of Fireface series, asynchronous transaction includes
a prefix byte to indicate the way to decode included MIDI bytes.
Upper 4 bits of the prefix byte indicates port number, and the rest 4
bits indicate the way to decode rest of bytes for MIDI messages.
Basically the rest bits indicates the number of bytes for MIDI message.
However, if the last byte of each MIDi message is included, the rest
bits are 0xf. For example:
message: f0 00 00 66 14 20 00 00 f7
offset: content (big endian, port 0)
'0030: 0x02f00000
'0030: 0x03006614
'0030: 0x03200000
'0030: 0x0ff70000
This commit supports encoding scheme for the above and allows
applications to transfer MIDI messages via ALSA rawmidi interface.
An unused member (running_status) is reused to keep state of
transmission of system exclusive messages.
For your information, this is a dump of config rom.
$ sudo ./hinawa-config-rom-printer /dev/fw1
{ 'bus-info': { 'bmc': False,
'chip_ID': 13225063715,
'cmc': False,
'cyc_clk_acc': 0,
'imc': False,
'isc': True,
'max_rec': 512,
'name': '1394',
'node_vendor_ID': 2613},
'root-directory': [ [ 'NODE_CAPABILITIES',
{ 'addressing': {'64': True, 'fix': True, 'prv': False},
'misc': {'int': False, 'ms': False, 'spt': True},
'state': { 'atn': False,
'ded': False,
'drq': True,
'elo': False,
'init': False,
'lst': True,
'off': False},
'testing': {'bas': False, 'ext': False}}],
['VENDOR', 2613],
['DESCRIPTOR', 'RME!'],
['EUI_64', 2873037108442403],
[ 'UNIT',
[ ['SPECIFIER_ID', 2613],
['VERSION', 4],
['MODEL', 1054720],
['DESCRIPTOR', 'Fireface UCX']]]]}
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:05 +07:00
|
|
|
/*
|
|
|
|
* When return minus value, given argument is not MIDI status.
|
|
|
|
* When return 0, given argument is a beginning of system exclusive.
|
|
|
|
* When return the others, given argument is MIDI data.
|
|
|
|
*/
|
|
|
|
static inline int calculate_message_bytes(u8 status)
|
|
|
|
{
|
|
|
|
switch (status) {
|
|
|
|
case 0xf6: /* Tune request. */
|
|
|
|
case 0xf8: /* Timing clock. */
|
|
|
|
case 0xfa: /* Start. */
|
|
|
|
case 0xfb: /* Continue. */
|
|
|
|
case 0xfc: /* Stop. */
|
|
|
|
case 0xfe: /* Active sensing. */
|
|
|
|
case 0xff: /* System reset. */
|
|
|
|
return 1;
|
|
|
|
case 0xf1: /* MIDI time code quarter frame. */
|
|
|
|
case 0xf3: /* Song select. */
|
|
|
|
return 2;
|
|
|
|
case 0xf2: /* Song position pointer. */
|
|
|
|
return 3;
|
|
|
|
case 0xf0: /* Exclusive. */
|
|
|
|
return 0;
|
|
|
|
case 0xf7: /* End of exclusive. */
|
|
|
|
break;
|
|
|
|
case 0xf4: /* Undefined. */
|
|
|
|
case 0xf5: /* Undefined. */
|
|
|
|
case 0xf9: /* Undefined. */
|
|
|
|
case 0xfd: /* Undefined. */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
switch (status & 0xf0) {
|
|
|
|
case 0x80: /* Note on. */
|
|
|
|
case 0x90: /* Note off. */
|
|
|
|
case 0xa0: /* Polyphonic key pressure. */
|
|
|
|
case 0xb0: /* Control change and Mode change. */
|
|
|
|
case 0xe0: /* Pitch bend change. */
|
|
|
|
return 3;
|
|
|
|
case 0xc0: /* Program change. */
|
|
|
|
case 0xd0: /* Channel pressure. */
|
|
|
|
return 2;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int latter_fill_midi_msg(struct snd_ff *ff,
|
|
|
|
struct snd_rawmidi_substream *substream,
|
|
|
|
unsigned int port)
|
|
|
|
{
|
|
|
|
u32 data = {0};
|
|
|
|
u8 *buf = (u8 *)&data;
|
|
|
|
int consumed;
|
|
|
|
|
|
|
|
buf[0] = port << 4;
|
|
|
|
consumed = snd_rawmidi_transmit_peek(substream, buf + 1, 3);
|
|
|
|
if (consumed <= 0)
|
|
|
|
return consumed;
|
|
|
|
|
|
|
|
if (!ff->on_sysex[port]) {
|
|
|
|
if (buf[1] != 0xf0) {
|
|
|
|
if (consumed < calculate_message_bytes(buf[1]))
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
// The beginning of exclusives.
|
|
|
|
ff->on_sysex[port] = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
buf[0] |= consumed;
|
|
|
|
} else {
|
|
|
|
if (buf[1] != 0xf7) {
|
|
|
|
if (buf[2] == 0xf7 || buf[3] == 0xf7) {
|
|
|
|
// Transfer end code at next time.
|
|
|
|
consumed -= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
buf[0] |= consumed;
|
|
|
|
} else {
|
|
|
|
// The end of exclusives.
|
|
|
|
ff->on_sysex[port] = false;
|
|
|
|
consumed = 1;
|
|
|
|
buf[0] |= 0x0f;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ff->msg_buf[port][0] = cpu_to_le32(data);
|
|
|
|
ff->rx_bytes[port] = consumed;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2019-01-20 15:25:53 +07:00
|
|
|
const struct snd_ff_protocol snd_ff_protocol_latter = {
|
ALSA: fireface: support tx MIDI functionality of Fireface UCX
Fireface UCX transfers asynchronous transactions for MIDI messages.
One transaction includes quadlet data therefore it can transfer 3
message bytes as maximum. Base address of the destination is
configured by two settings; a register for higher 8 byte of the
address, and a bitflag to option register indicates lower 8byte.
The register for higher address is 0x'ffff'0000'0034. Unfortunately,
firmware v24 includes a bug to ignore registered value for the
destination address and transfers to 0x0001xxxxxxxx always. This
driver doesn't work well if the bug exists, therefore users should
install the latest firmware (v27).
The bitflag is a part of value to be written to option register
(0x'ffff'0000'0014).
lower addr: bitflag (little endian)
'0000'0000: 0x00002000
'0000'0080: 0x00004000
'0000'0100: 0x00008000
'0000'0180: 0x00010000
This register includes more options but they are not relevant to
packet streaming or MIDI functionality. This driver don't touch it.
Furthermore, the transaction is sent to address offset incremented
by 4 byte to the offset in previous time. When it reaches base address
plus 0x7c, next offset is the base address.
Content of the transaction includes a prefix byte. Upper 4 bits of
the byte indicates port number, and the rest 4 bits indicate the way
to decode rest of bytes for MIDI message.
Except for system exclusive messages, the rest bits are the same as
status bits of the message without channel bits. For system exclusive
messages, the rest bits are encoded according to included message bytes.
For example:
message: f0 7e 7f 09 01 f7
offset: content (little endian, port 0)
'0000: 0x04f07e7f
'0004: 0x070901f7
message: f0 00 00 66 14 20 00 00 00 f7
offset: content (little endian, port 1)
'0014: 0x14f00000
'0018: 0x14661420
'001c: 0x14000000
'0020: 0x15f70000
message: f0 00 00 66 14 20 00 00 f7
offset: content (little endian, port 0)
'0078: 0x04f00000
'007c: 0x04661420
'0000: 0x070000f7
This commit supports decoding scheme for the above and allows
applications to receive MIDI messages via ALSA rawmidi interface.
The lower 8 bytes of destination address is fixed to 0x'0000'0000,
thus this driver expects userspace applications to configure option
register with bitflag 0x00002000 in advance.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:02 +07:00
|
|
|
.handle_midi_msg = latter_handle_midi_msg,
|
ALSA: fireface: support rx MIDI functionality for Fireface UCX
In latter model of Fireface series, asynchronous transaction includes
a prefix byte to indicate the way to decode included MIDI bytes.
Upper 4 bits of the prefix byte indicates port number, and the rest 4
bits indicate the way to decode rest of bytes for MIDI messages.
Basically the rest bits indicates the number of bytes for MIDI message.
However, if the last byte of each MIDi message is included, the rest
bits are 0xf. For example:
message: f0 00 00 66 14 20 00 00 f7
offset: content (big endian, port 0)
'0030: 0x02f00000
'0030: 0x03006614
'0030: 0x03200000
'0030: 0x0ff70000
This commit supports encoding scheme for the above and allows
applications to transfer MIDI messages via ALSA rawmidi interface.
An unused member (running_status) is reused to keep state of
transmission of system exclusive messages.
For your information, this is a dump of config rom.
$ sudo ./hinawa-config-rom-printer /dev/fw1
{ 'bus-info': { 'bmc': False,
'chip_ID': 13225063715,
'cmc': False,
'cyc_clk_acc': 0,
'imc': False,
'isc': True,
'max_rec': 512,
'name': '1394',
'node_vendor_ID': 2613},
'root-directory': [ [ 'NODE_CAPABILITIES',
{ 'addressing': {'64': True, 'fix': True, 'prv': False},
'misc': {'int': False, 'ms': False, 'spt': True},
'state': { 'atn': False,
'ded': False,
'drq': True,
'elo': False,
'init': False,
'lst': True,
'off': False},
'testing': {'bas': False, 'ext': False}}],
['VENDOR', 2613],
['DESCRIPTOR', 'RME!'],
['EUI_64', 2873037108442403],
[ 'UNIT',
[ ['SPECIFIER_ID', 2613],
['VERSION', 4],
['MODEL', 1054720],
['DESCRIPTOR', 'Fireface UCX']]]]}
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2019-01-22 20:17:05 +07:00
|
|
|
.fill_midi_msg = latter_fill_midi_msg,
|
2019-01-20 15:25:53 +07:00
|
|
|
.get_clock = latter_get_clock,
|
|
|
|
.switch_fetching_mode = latter_switch_fetching_mode,
|
|
|
|
.begin_session = latter_begin_session,
|
|
|
|
.finish_session = latter_finish_session,
|
|
|
|
.dump_status = latter_dump_status,
|
|
|
|
};
|