2016-07-05 23:40:49 +07:00
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Ping Gao <ping.a.gao@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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2016-10-20 16:15:03 +07:00
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#include "gvt.h"
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#include "i915_pvinfo.h"
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2016-07-05 23:40:49 +07:00
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2016-10-26 08:38:52 +07:00
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void populate_pvinfo_page(struct intel_vgpu *vgpu)
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2016-07-05 23:40:49 +07:00
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{
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/* setup the ballooning information */
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vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
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vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
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vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
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vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
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vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
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2017-08-14 14:24:14 +07:00
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vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
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2016-07-05 23:40:49 +07:00
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
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vgpu_aperture_gmadr_base(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
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vgpu_aperture_sz(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
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vgpu_hidden_gmadr_base(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
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vgpu_hidden_sz(vgpu);
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vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
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gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
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gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
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vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
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gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
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vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
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gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
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WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
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}
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2017-03-29 23:36:37 +07:00
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#define VGPU_MAX_WEIGHT 16
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#define VGPU_WEIGHT(vgpu_num) \
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(VGPU_MAX_WEIGHT / (vgpu_num))
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2017-02-23 13:46:23 +07:00
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static struct {
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unsigned int low_mm;
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unsigned int high_mm;
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unsigned int fence;
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2017-03-29 23:36:37 +07:00
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/* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
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* with a weight of 4 on a contended host, different vGPU type has
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* different weight set. Legal weights range from 1 to 16.
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*/
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unsigned int weight;
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2017-02-24 09:58:21 +07:00
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enum intel_vgpu_edid edid;
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2017-02-23 13:46:23 +07:00
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char *name;
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} vgpu_types[] = {
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/* Fixed vGPU type table */
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2017-03-29 23:36:37 +07:00
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{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
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{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
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{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
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{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
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2017-02-23 13:46:23 +07:00
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};
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2016-11-03 17:38:31 +07:00
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/**
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* intel_gvt_init_vgpu_types - initialize vGPU type list
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* @gvt : GVT device
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*
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* Initialize vGPU type list based on available resource.
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*
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*/
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int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
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{
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unsigned int num_types;
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2017-01-13 14:36:17 +07:00
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unsigned int i, low_avail, high_avail;
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2016-11-03 17:38:31 +07:00
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unsigned int min_low;
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/* vGPU type name is defined as GVTg_Vx_y which contains
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2017-02-23 13:46:23 +07:00
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* physical GPU generation type (e.g V4 as BDW server, V5 as
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* SKL server).
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2016-11-03 17:38:31 +07:00
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*
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* Depend on physical SKU resource, might see vGPU types like
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* GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
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* different types of vGPU on same physical GPU depending on
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* available resource. Each vGPU type will have "avail_instance"
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* to indicate how many vGPU instance can be created for this
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* type.
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*
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*/
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2017-01-13 14:36:17 +07:00
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low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
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high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
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2017-02-23 13:46:23 +07:00
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num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
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2016-11-03 17:38:31 +07:00
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gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
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GFP_KERNEL);
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if (!gvt->types)
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return -ENOMEM;
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min_low = MB_TO_BYTES(32);
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for (i = 0; i < num_types; ++i) {
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2017-02-23 13:46:23 +07:00
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if (low_avail / vgpu_types[i].low_mm == 0)
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2016-11-03 17:38:31 +07:00
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break;
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2017-02-23 13:46:23 +07:00
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gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
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gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
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gvt->types[i].fence = vgpu_types[i].fence;
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2017-03-29 23:36:37 +07:00
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if (vgpu_types[i].weight < 1 ||
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vgpu_types[i].weight > VGPU_MAX_WEIGHT)
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return -EINVAL;
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gvt->types[i].weight = vgpu_types[i].weight;
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2017-02-24 09:58:21 +07:00
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gvt->types[i].resolution = vgpu_types[i].edid;
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2017-02-23 13:46:23 +07:00
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gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
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high_avail / vgpu_types[i].high_mm);
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2016-11-03 17:38:31 +07:00
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if (IS_GEN8(gvt->dev_priv))
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2017-02-23 13:46:23 +07:00
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sprintf(gvt->types[i].name, "GVTg_V4_%s",
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vgpu_types[i].name);
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2016-11-03 17:38:31 +07:00
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else if (IS_GEN9(gvt->dev_priv))
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2017-02-23 13:46:23 +07:00
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sprintf(gvt->types[i].name, "GVTg_V5_%s",
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vgpu_types[i].name);
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2016-11-03 17:38:31 +07:00
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2017-03-29 23:36:37 +07:00
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gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
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2017-02-23 13:46:23 +07:00
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i, gvt->types[i].name,
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2016-11-03 17:38:31 +07:00
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gvt->types[i].avail_instance,
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gvt->types[i].low_gm_size,
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2017-02-24 09:58:21 +07:00
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gvt->types[i].high_gm_size, gvt->types[i].fence,
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2017-03-29 23:36:37 +07:00
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gvt->types[i].weight,
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2017-02-24 09:58:21 +07:00
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vgpu_edid_str(gvt->types[i].resolution));
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2016-11-03 17:38:31 +07:00
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}
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gvt->num_types = i;
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return 0;
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}
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void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
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{
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kfree(gvt->types);
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}
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static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
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{
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int i;
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unsigned int low_gm_avail, high_gm_avail, fence_avail;
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2017-02-23 13:46:23 +07:00
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unsigned int low_gm_min, high_gm_min, fence_min;
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2016-11-03 17:38:31 +07:00
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/* Need to depend on maxium hw resource size but keep on
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* static config for now.
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*/
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2017-01-13 14:36:17 +07:00
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low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
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2016-11-03 17:38:31 +07:00
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gvt->gm.vgpu_allocated_low_gm_size;
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2017-01-13 14:36:17 +07:00
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high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
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2016-11-03 17:38:31 +07:00
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gvt->gm.vgpu_allocated_high_gm_size;
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fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
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gvt->fence.vgpu_allocated_fence_num;
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for (i = 0; i < gvt->num_types; i++) {
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low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
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high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
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fence_min = fence_avail / gvt->types[i].fence;
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2017-02-23 13:46:23 +07:00
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gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
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fence_min);
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2016-11-03 17:38:31 +07:00
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2017-02-23 13:46:23 +07:00
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gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
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i, gvt->types[i].name,
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2016-11-03 17:38:31 +07:00
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gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
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gvt->types[i].high_gm_size, gvt->types[i].fence);
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}
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}
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2016-07-05 23:40:49 +07:00
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/**
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2017-03-30 00:48:39 +07:00
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* intel_gvt_active_vgpu - activate a virtual GPU
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2016-07-05 23:40:49 +07:00
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* @vgpu: virtual GPU
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*
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2017-03-30 00:48:39 +07:00
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* This function is called when user wants to activate a virtual GPU.
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2016-07-05 23:40:49 +07:00
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*
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*/
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2017-03-30 00:48:39 +07:00
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void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
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{
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mutex_lock(&vgpu->gvt->lock);
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vgpu->active = true;
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mutex_unlock(&vgpu->gvt->lock);
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}
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/**
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* intel_gvt_deactive_vgpu - deactivate a virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to deactivate a virtual GPU.
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* All virtual GPU runtime information will be destroyed.
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*
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*/
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void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
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2016-07-05 23:40:49 +07:00
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{
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struct intel_gvt *gvt = vgpu->gvt;
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mutex_lock(&gvt->lock);
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vgpu->active = false;
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2016-05-02 04:09:58 +07:00
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if (atomic_read(&vgpu->running_workload_num)) {
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mutex_unlock(&gvt->lock);
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intel_gvt_wait_vgpu_idle(vgpu);
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mutex_lock(&gvt->lock);
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}
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intel_vgpu_stop_schedule(vgpu);
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2017-03-30 00:48:39 +07:00
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mutex_unlock(&gvt->lock);
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}
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/**
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* intel_gvt_destroy_vgpu - destroy a virtual GPU
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* @vgpu: virtual GPU
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*
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* This function is called when user wants to destroy a virtual GPU.
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*
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*/
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void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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mutex_lock(&gvt->lock);
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WARN(vgpu->active, "vGPU is still active!\n");
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idr_remove(&gvt->vgpu_idr, vgpu->id);
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2016-05-02 04:09:58 +07:00
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intel_vgpu_clean_sched_policy(vgpu);
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2017-09-10 19:08:18 +07:00
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intel_vgpu_clean_submission(vgpu);
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2016-05-01 16:22:47 +07:00
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intel_vgpu_clean_execlist(vgpu);
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2016-04-26 05:28:56 +07:00
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intel_vgpu_clean_display(vgpu);
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2016-07-20 12:14:38 +07:00
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intel_vgpu_clean_opregion(vgpu);
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2016-03-28 22:23:16 +07:00
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intel_vgpu_clean_gtt(vgpu);
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2016-07-05 23:40:49 +07:00
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intel_gvt_hypervisor_detach_vgpu(vgpu);
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intel_vgpu_free_resource(vgpu);
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2017-01-13 10:16:00 +07:00
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intel_vgpu_clean_mmio(vgpu);
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2016-07-05 23:40:49 +07:00
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vfree(vgpu);
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2016-11-03 17:38:31 +07:00
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intel_gvt_update_vgpu_types(gvt);
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2016-07-05 23:40:49 +07:00
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mutex_unlock(&gvt->lock);
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}
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2017-03-29 23:36:39 +07:00
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#define IDLE_VGPU_IDR 0
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/**
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* intel_gvt_create_idle_vgpu - create an idle virtual GPU
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* @gvt: GVT device
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*
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* This function is called when user wants to create an idle virtual GPU.
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*
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* Returns:
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* pointer to intel_vgpu, error pointer if failed.
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*/
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struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
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{
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|
|
|
struct intel_vgpu *vgpu;
|
|
|
|
enum intel_engine_id i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
vgpu = vzalloc(sizeof(*vgpu));
|
|
|
|
if (!vgpu)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
vgpu->id = IDLE_VGPU_IDR;
|
|
|
|
vgpu->gvt = gvt;
|
|
|
|
|
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++)
|
|
|
|
INIT_LIST_HEAD(&vgpu->workload_q_head[i]);
|
|
|
|
|
|
|
|
ret = intel_vgpu_init_sched_policy(vgpu);
|
|
|
|
if (ret)
|
|
|
|
goto out_free_vgpu;
|
|
|
|
|
|
|
|
vgpu->active = false;
|
|
|
|
|
|
|
|
return vgpu;
|
|
|
|
|
|
|
|
out_free_vgpu:
|
|
|
|
vfree(vgpu);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_gvt_destroy_vgpu - destroy an idle virtual GPU
|
|
|
|
* @vgpu: virtual GPU
|
|
|
|
*
|
|
|
|
* This function is called when user wants to destroy an idle virtual GPU.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
|
|
|
|
{
|
|
|
|
intel_vgpu_clean_sched_policy(vgpu);
|
|
|
|
vfree(vgpu);
|
|
|
|
}
|
|
|
|
|
2016-11-03 17:38:31 +07:00
|
|
|
static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
|
2016-07-05 23:40:49 +07:00
|
|
|
struct intel_vgpu_creation_params *param)
|
|
|
|
{
|
|
|
|
struct intel_vgpu *vgpu;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
|
|
|
|
param->handle, param->low_gm_sz, param->high_gm_sz,
|
|
|
|
param->fence_sz);
|
|
|
|
|
|
|
|
vgpu = vzalloc(sizeof(*vgpu));
|
|
|
|
if (!vgpu)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
mutex_lock(&gvt->lock);
|
|
|
|
|
2017-03-29 23:36:39 +07:00
|
|
|
ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
|
|
|
|
GFP_KERNEL);
|
2016-07-05 23:40:49 +07:00
|
|
|
if (ret < 0)
|
|
|
|
goto out_free_vgpu;
|
|
|
|
|
|
|
|
vgpu->id = ret;
|
|
|
|
vgpu->handle = param->handle;
|
|
|
|
vgpu->gvt = gvt;
|
2017-03-29 23:36:37 +07:00
|
|
|
vgpu->sched_ctl.weight = param->weight;
|
2016-05-02 06:02:37 +07:00
|
|
|
bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
|
2016-07-05 23:40:49 +07:00
|
|
|
|
2017-01-13 10:15:58 +07:00
|
|
|
intel_vgpu_init_cfg_space(vgpu, param->primary);
|
2016-07-05 23:40:49 +07:00
|
|
|
|
2017-01-13 10:16:00 +07:00
|
|
|
ret = intel_vgpu_init_mmio(vgpu);
|
2016-07-05 23:40:49 +07:00
|
|
|
if (ret)
|
2017-01-06 14:16:22 +07:00
|
|
|
goto out_clean_idr;
|
2016-07-05 23:40:49 +07:00
|
|
|
|
|
|
|
ret = intel_vgpu_alloc_resource(vgpu, param);
|
|
|
|
if (ret)
|
|
|
|
goto out_clean_vgpu_mmio;
|
|
|
|
|
|
|
|
populate_pvinfo_page(vgpu);
|
|
|
|
|
|
|
|
ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
|
|
|
|
if (ret)
|
|
|
|
goto out_clean_vgpu_resource;
|
|
|
|
|
2016-03-28 22:23:16 +07:00
|
|
|
ret = intel_vgpu_init_gtt(vgpu);
|
|
|
|
if (ret)
|
|
|
|
goto out_detach_hypervisor_vgpu;
|
|
|
|
|
2017-02-24 09:58:21 +07:00
|
|
|
ret = intel_vgpu_init_display(vgpu, param->resolution);
|
2016-04-26 05:28:56 +07:00
|
|
|
if (ret)
|
2016-11-03 17:38:32 +07:00
|
|
|
goto out_clean_gtt;
|
2016-04-26 05:28:56 +07:00
|
|
|
|
2016-05-01 13:48:25 +07:00
|
|
|
ret = intel_vgpu_init_execlist(vgpu);
|
|
|
|
if (ret)
|
|
|
|
goto out_clean_display;
|
|
|
|
|
2017-09-10 19:08:18 +07:00
|
|
|
ret = intel_vgpu_setup_submission(vgpu);
|
2016-05-01 18:42:16 +07:00
|
|
|
if (ret)
|
|
|
|
goto out_clean_execlist;
|
|
|
|
|
2016-05-02 04:09:58 +07:00
|
|
|
ret = intel_vgpu_init_sched_policy(vgpu);
|
|
|
|
if (ret)
|
|
|
|
goto out_clean_shadow_ctx;
|
|
|
|
|
2016-07-05 23:40:49 +07:00
|
|
|
mutex_unlock(&gvt->lock);
|
|
|
|
|
|
|
|
return vgpu;
|
|
|
|
|
2016-05-02 04:09:58 +07:00
|
|
|
out_clean_shadow_ctx:
|
2017-09-10 19:08:18 +07:00
|
|
|
intel_vgpu_clean_submission(vgpu);
|
2016-05-01 18:42:16 +07:00
|
|
|
out_clean_execlist:
|
|
|
|
intel_vgpu_clean_execlist(vgpu);
|
2016-05-01 13:48:25 +07:00
|
|
|
out_clean_display:
|
|
|
|
intel_vgpu_clean_display(vgpu);
|
2016-07-20 12:14:38 +07:00
|
|
|
out_clean_gtt:
|
|
|
|
intel_vgpu_clean_gtt(vgpu);
|
2016-03-28 22:23:16 +07:00
|
|
|
out_detach_hypervisor_vgpu:
|
|
|
|
intel_gvt_hypervisor_detach_vgpu(vgpu);
|
2016-07-05 23:40:49 +07:00
|
|
|
out_clean_vgpu_resource:
|
|
|
|
intel_vgpu_free_resource(vgpu);
|
|
|
|
out_clean_vgpu_mmio:
|
2017-01-13 10:16:00 +07:00
|
|
|
intel_vgpu_clean_mmio(vgpu);
|
2017-01-06 14:16:22 +07:00
|
|
|
out_clean_idr:
|
|
|
|
idr_remove(&gvt->vgpu_idr, vgpu->id);
|
2016-07-05 23:40:49 +07:00
|
|
|
out_free_vgpu:
|
|
|
|
vfree(vgpu);
|
|
|
|
mutex_unlock(&gvt->lock);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2016-11-03 17:38:31 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_gvt_create_vgpu - create a virtual GPU
|
|
|
|
* @gvt: GVT device
|
|
|
|
* @type: type of the vGPU to create
|
|
|
|
*
|
|
|
|
* This function is called when user wants to create a virtual GPU.
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* pointer to intel_vgpu, error pointer if failed.
|
|
|
|
*/
|
|
|
|
struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
|
|
|
|
struct intel_vgpu_type *type)
|
|
|
|
{
|
|
|
|
struct intel_vgpu_creation_params param;
|
|
|
|
struct intel_vgpu *vgpu;
|
|
|
|
|
|
|
|
param.handle = 0;
|
2016-11-21 16:08:14 +07:00
|
|
|
param.primary = 1;
|
2016-11-03 17:38:31 +07:00
|
|
|
param.low_gm_sz = type->low_gm_size;
|
|
|
|
param.high_gm_sz = type->high_gm_size;
|
|
|
|
param.fence_sz = type->fence;
|
2017-03-29 23:36:37 +07:00
|
|
|
param.weight = type->weight;
|
2017-02-24 09:58:21 +07:00
|
|
|
param.resolution = type->resolution;
|
2016-11-03 17:38:31 +07:00
|
|
|
|
|
|
|
/* XXX current param based on MB */
|
|
|
|
param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
|
|
|
|
param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
|
|
|
|
|
|
|
|
vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
|
|
|
|
if (IS_ERR(vgpu))
|
|
|
|
return vgpu;
|
|
|
|
|
|
|
|
/* calculate left instance change for types */
|
|
|
|
intel_gvt_update_vgpu_types(gvt);
|
|
|
|
|
|
|
|
return vgpu;
|
|
|
|
}
|
2016-11-03 17:38:35 +07:00
|
|
|
|
|
|
|
/**
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
* intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
|
|
|
|
* @vgpu: virtual GPU
|
|
|
|
* @dmlr: vGPU Device Model Level Reset or GT Reset
|
|
|
|
* @engine_mask: engines to reset for GT reset
|
|
|
|
*
|
|
|
|
* This function is called when user wants to reset a virtual GPU through
|
|
|
|
* device model reset or GT reset. The caller should hold the gvt lock.
|
|
|
|
*
|
|
|
|
* vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
|
|
|
|
* the whole vGPU to default state as when it is created. This vGPU function
|
|
|
|
* is required both for functionary and security concerns.The ultimate goal
|
|
|
|
* of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
|
|
|
|
* assign a vGPU to a virtual machine we must isse such reset first.
|
|
|
|
*
|
|
|
|
* Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
|
|
|
|
* (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
|
|
|
|
* Unlike the FLR, GT reset only reset particular resource of a vGPU per
|
|
|
|
* the reset request. Guest driver can issue a GT reset by programming the
|
|
|
|
* virtual GDRST register to reset specific virtual GPU engine or all
|
|
|
|
* engines.
|
|
|
|
*
|
|
|
|
* The parameter dev_level is to identify if we will do DMLR or GT reset.
|
|
|
|
* The parameter engine_mask is to specific the engines that need to be
|
|
|
|
* resetted. If value ALL_ENGINES is given for engine_mask, it means
|
|
|
|
* the caller requests a full GT reset that we will reset all virtual
|
|
|
|
* GPU engines. For FLR, engine_mask is ignored.
|
|
|
|
*/
|
|
|
|
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
|
|
|
|
unsigned int engine_mask)
|
|
|
|
{
|
|
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
|
|
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
2017-08-01 16:47:25 +07:00
|
|
|
unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
|
|
|
|
gvt_dbg_core("------------------------------------------\n");
|
|
|
|
gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
|
|
|
|
vgpu->id, dmlr, engine_mask);
|
2017-08-01 16:47:25 +07:00
|
|
|
|
|
|
|
vgpu->resetting_eng = resetting_eng;
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
|
|
|
|
intel_vgpu_stop_schedule(vgpu);
|
|
|
|
/*
|
|
|
|
* The current_vgpu will set to NULL after stopping the
|
|
|
|
* scheduler when the reset is triggered by current vgpu.
|
|
|
|
*/
|
|
|
|
if (scheduler->current_vgpu == NULL) {
|
|
|
|
mutex_unlock(&gvt->lock);
|
|
|
|
intel_gvt_wait_vgpu_idle(vgpu);
|
|
|
|
mutex_lock(&gvt->lock);
|
|
|
|
}
|
|
|
|
|
2017-08-01 16:47:25 +07:00
|
|
|
intel_vgpu_reset_execlist(vgpu, resetting_eng);
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
|
|
|
|
/* full GPU reset or device model level reset */
|
|
|
|
if (engine_mask == ALL_ENGINES || dmlr) {
|
2017-05-25 14:33:52 +07:00
|
|
|
|
|
|
|
/*fence will not be reset during virtual reset */
|
2017-08-04 12:08:59 +07:00
|
|
|
if (dmlr) {
|
|
|
|
intel_vgpu_reset_gtt(vgpu);
|
2017-05-25 14:33:52 +07:00
|
|
|
intel_vgpu_reset_resource(vgpu);
|
2017-08-04 12:08:59 +07:00
|
|
|
}
|
2017-05-25 14:33:52 +07:00
|
|
|
|
|
|
|
intel_vgpu_reset_mmio(vgpu, dmlr);
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
populate_pvinfo_page(vgpu);
|
2017-02-14 13:50:18 +07:00
|
|
|
intel_vgpu_reset_display(vgpu);
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
|
2017-02-17 14:02:36 +07:00
|
|
|
if (dmlr) {
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
intel_vgpu_reset_cfg_space(vgpu);
|
2017-02-17 14:02:36 +07:00
|
|
|
/* only reset the failsafe mode when dmlr reset */
|
|
|
|
vgpu->failsafe = false;
|
|
|
|
vgpu->pv_notified = false;
|
|
|
|
}
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
}
|
|
|
|
|
2017-08-01 16:47:25 +07:00
|
|
|
vgpu->resetting_eng = 0;
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
|
|
|
|
gvt_dbg_core("------------------------------------------\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
|
2016-11-03 17:38:35 +07:00
|
|
|
* @vgpu: virtual GPU
|
|
|
|
*
|
|
|
|
* This function is called when user wants to reset a virtual GPU.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
|
|
|
|
{
|
drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function
Our function tests found several issues related to reusing vGPU
instance. They are qemu reboot failure, guest tdr after reboot, host
hang when reboot guest. All these issues are caused by dirty status
inherited from last VM.
This patch fix all these issues by resetting a virtual GPU before VM
use it. The reset logical is put into a low level function
_intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
GT Reset and Per-Engine Reset.
vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
the whole vGPU to default state as when it is created, including GTT,
execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
and fence registers. The ultimate goal of vGPU DMLR is that reuse a
vGPU instance by different virtual machines. When we reassign a vGPU
to a virtual machine we must issue such reset first.
Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
(Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
Unlike the FLR, GT reset only reset particular resource of a vGPU per
the reset request. Guest driver can issue a GT reset by programming
the virtual GDRST register to reset specific virtual GPU engine or all
engines.
Since vGPU DMLR and GT reset can share some code so we implement both
these two into one single function intel_gvt_reset_vgpu_locked(). The
parameter dmlr is to identify if we will do FLR or GT reset. The
parameter engine_mask is to specific the engines that need to be
resetted. If value ALL_ENGINES is given for engine_mask, it means
the caller requests a full gt reset that we will reset all virtual
GPU engines.
Signed-off-by: Changbin Du <changbin.du@intel.com>
Reviewed-by: Jike Song <jike.song@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-01-13 10:16:02 +07:00
|
|
|
mutex_lock(&vgpu->gvt->lock);
|
|
|
|
intel_gvt_reset_vgpu_locked(vgpu, true, 0);
|
|
|
|
mutex_unlock(&vgpu->gvt->lock);
|
2016-11-03 17:38:35 +07:00
|
|
|
}
|