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linux_dsm_epyc7002/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi

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arm64: tegra: Add PMIC support on Jetson TX1 Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23 22:20:35 +07:00
#include <dt-bindings/mfd/max77620.h>
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
#include "tegra210.dtsi"
/ {
model = "NVIDIA Jetson TX1";
compatible = "nvidia,p2180", "nvidia,tegra210";
aliases {
arm64: tegra: Add PMIC support on Jetson TX1 Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23 22:20:35 +07:00
rtc0 = "/i2c@7000d000/pmic@3c";
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
rtc1 = "/rtc@7000e000";
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
serial0 = &uarta;
};
arm64: tegra: Enable debug serial on Jetson TX1 Add a chosen node to the device tree that contains a stdout-path property which defines the debug serial port. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-02 19:07:47 +07:00
chosen {
stdout-path = "serial0:115200n8";
};
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
};
/* debug port */
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
serial@70006000 {
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
status = "okay";
};
arm64: tegra: Add PMIC support on Jetson TX1 Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-23 22:20:35 +07:00
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
};
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
};
gpio2_3 {
pins = "gpio2", "gpio3";
function = "fps-out";
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
gpio4 {
pins = "gpio4";
function = "32k-out1";
};
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull = <1>;
};
};
fps {
fps0 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
maxim,suspend-fps-time-period-us = <1280>;
};
fps1 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
maxim,suspend-fps-time-period-us = <1280>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
};
regulators {
in-ldo0-1-supply = <&vdd_pre>;
in-ldo7-8-supply = <&vdd_pre>;
in-sd3-supply = <&vdd_5v0_sys>;
vdd_soc: sd0 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <146>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vdd_ddr: sd1 {
regulator-name = "VDD_DDR_1V1_PMIC";
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <130>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_pre: sd2 {
regulator-name = "VDD_PRE_REG_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-enable-ramp-delay = <176>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vdd_1v8: sd3 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <242>;
regulator-ramp-delay = <27500>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_sys_1v2: ldo0 {
regulator-name = "AVDD_SYS_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <26>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_pex_1v05: ldo1 {
regulator-name = "VDD_PEX_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
vddio_sdmmc: ldo2 {
regulator-name = "VDDIO_SDMMC";
/*
* Technically this supply should have
* a supported range from 1.8 - 3.3 V.
* However, that would cause the SDHCI
* driver to request 2.7 V upon access
* and that in turn will cause traffic
* to be broken. Leave it at 3.3 V for
* now.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_cam_hv: ldo3 {
regulator-name = "VDD_CAM_HV";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <50>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_rtc: ldo4 {
regulator-name = "VDD_RTC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
vdd_ts_hv: ldo5 {
regulator-name = "VDD_TS_HV";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <62>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
vdd_ts: ldo6 {
regulator-name = "VDD_TS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <36>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
};
avdd_1v05_pll: ldo7 {
regulator-name = "AVDD_1V05_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
regulator-enable-ramp-delay = <24>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
avdd_1v05: ldo8 {
regulator-name = "AVDD_SATA_HDMI_DP_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-enable-ramp-delay = <22>;
regulator-ramp-delay = <100000>;
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
};
};
};
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
pmc@7000e400 {
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
nvidia,invert-interrupt;
};
/* eMMC */
arm64: tegra: Remove 0, prefix from unit-addresses When Tegra124 support was first merged the unit-addresses of all devices were listed with a "0," prefix to encode the reg property's second cell. It turns out that this notation is not correct, and the "," separator is only used to separate fields in the unit address (such as the device and function number in PCI devices), not individual cells for addresses with more than one cell. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 20:35:06 +07:00
sdhci@700b0600 {
arm64: tegra: Add NVIDIA Jetson TX1 support The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 21:25:05 +07:00
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};
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