2014-10-08 15:55:02 +07:00
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/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/mutex.h>
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#include <linux/mm.h>
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#include <linux/uaccess.h>
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#include <asm/synch.h>
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2015-05-27 13:07:16 +07:00
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#include <misc/cxl-base.h>
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2014-10-08 15:55:02 +07:00
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#include "cxl.h"
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2015-01-09 16:34:36 +07:00
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#include "trace.h"
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2014-10-08 15:55:02 +07:00
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static int afu_control(struct cxl_afu *afu, u64 command,
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u64 result, u64 mask, bool enabled)
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{
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u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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2015-01-09 16:34:36 +07:00
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int rc = 0;
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2014-10-08 15:55:02 +07:00
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spin_lock(&afu->afu_cntl_lock);
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pr_devel("AFU command starting: %llx\n", command);
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2015-01-09 16:34:36 +07:00
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trace_cxl_afu_ctrl(afu, command);
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2014-10-08 15:55:02 +07:00
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cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command);
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AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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while ((AFU_Cntl & mask) != result) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
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2015-01-09 16:34:36 +07:00
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rc = -EBUSY;
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goto out;
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2014-10-08 15:55:02 +07:00
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}
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(afu->adapter)) {
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afu->enabled = enabled;
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rc = -EIO;
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goto out;
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}
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2015-06-11 18:27:52 +07:00
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pr_devel_ratelimited("AFU control... (0x%016llx)\n",
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2014-10-08 15:55:02 +07:00
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AFU_Cntl | command);
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cpu_relax();
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AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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};
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pr_devel("AFU command complete: %llx\n", command);
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afu->enabled = enabled;
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2015-01-09 16:34:36 +07:00
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out:
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trace_cxl_afu_ctrl_done(afu, command, rc);
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2014-10-08 15:55:02 +07:00
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spin_unlock(&afu->afu_cntl_lock);
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2015-01-09 16:34:36 +07:00
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return rc;
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2014-10-08 15:55:02 +07:00
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}
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static int afu_enable(struct cxl_afu *afu)
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{
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pr_devel("AFU enable request\n");
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return afu_control(afu, CXL_AFU_Cntl_An_E,
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CXL_AFU_Cntl_An_ES_Enabled,
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CXL_AFU_Cntl_An_ES_MASK, true);
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}
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int cxl_afu_disable(struct cxl_afu *afu)
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{
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pr_devel("AFU disable request\n");
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return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled,
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CXL_AFU_Cntl_An_ES_MASK, false);
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}
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/* This will disable as well as reset */
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2015-05-27 13:07:09 +07:00
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int __cxl_afu_reset(struct cxl_afu *afu)
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2014-10-08 15:55:02 +07:00
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{
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pr_devel("AFU reset request\n");
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return afu_control(afu, CXL_AFU_Cntl_An_RA,
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CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
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CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
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false);
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}
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2015-05-27 13:07:10 +07:00
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int cxl_afu_check_and_enable(struct cxl_afu *afu)
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2014-10-08 15:55:02 +07:00
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{
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(afu->adapter)) {
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WARN(1, "Refusing to enable afu while link down!\n");
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return -EIO;
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}
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2014-10-08 15:55:02 +07:00
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if (afu->enabled)
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return 0;
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return afu_enable(afu);
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}
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int cxl_psl_purge(struct cxl_afu *afu)
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{
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u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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u64 dsisr, dar;
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u64 start, end;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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2015-01-09 16:34:36 +07:00
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int rc = 0;
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trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
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2014-10-08 15:55:02 +07:00
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pr_devel("PSL purge request\n");
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(afu->adapter)) {
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dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
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rc = -EIO;
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goto out;
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}
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2014-10-08 15:55:02 +07:00
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if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
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WARN(1, "psl_purge request while AFU not disabled!\n");
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cxl_afu_disable(afu);
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}
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cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
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PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
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start = local_clock();
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PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
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== CXL_PSL_SCNTL_An_Ps_Pending) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
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2015-01-09 16:34:36 +07:00
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rc = -EBUSY;
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goto out;
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2014-10-08 15:55:02 +07:00
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}
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(afu->adapter)) {
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rc = -EIO;
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goto out;
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}
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2014-10-08 15:55:02 +07:00
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dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
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2015-06-11 18:27:52 +07:00
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pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
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2014-10-08 15:55:02 +07:00
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if (dsisr & CXL_PSL_DSISR_TRANS) {
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dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
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2015-06-11 18:27:52 +07:00
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dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
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2014-10-08 15:55:02 +07:00
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
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} else if (dsisr) {
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2015-06-11 18:27:52 +07:00
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dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
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2014-10-08 15:55:02 +07:00
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
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} else {
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cpu_relax();
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}
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PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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};
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end = local_clock();
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pr_devel("PSL purged in %lld ns\n", end - start);
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cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
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PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
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2015-01-09 16:34:36 +07:00
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out:
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trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
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return rc;
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2014-10-08 15:55:02 +07:00
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}
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static int spa_max_procs(int spa_size)
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{
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/*
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* From the CAIA:
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* end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
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* Most of that junk is really just an overly-complicated way of saying
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* the last 256 bytes are __aligned(128), so it's really:
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* end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
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* and
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* end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
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* so
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* sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
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* Ignore the alignment (which is safe in this case as long as we are
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* careful with our rounding) and solve for n:
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*/
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return ((spa_size / 8) - 96) / 17;
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}
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2015-08-14 14:41:19 +07:00
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int cxl_alloc_spa(struct cxl_afu *afu)
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2014-10-08 15:55:02 +07:00
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{
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/* Work out how many pages to allocate */
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afu->spa_order = 0;
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do {
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afu->spa_order++;
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afu->spa_size = (1 << afu->spa_order) * PAGE_SIZE;
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afu->spa_max_procs = spa_max_procs(afu->spa_size);
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} while (afu->spa_max_procs < afu->num_procs);
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WARN_ON(afu->spa_size > 0x100000); /* Max size supported by the hardware */
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if (!(afu->spa = (struct cxl_process_element *)
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__get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->spa_order))) {
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pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
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return -ENOMEM;
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}
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pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
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1<<afu->spa_order, afu->spa_max_procs, afu->num_procs);
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2015-08-14 14:41:19 +07:00
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return 0;
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}
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static void attach_spa(struct cxl_afu *afu)
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{
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u64 spap;
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2014-10-08 15:55:02 +07:00
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afu->sw_command_status = (__be64 *)((char *)afu->spa +
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((afu->spa_max_procs + 3) * 128));
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spap = virt_to_phys(afu->spa) & CXL_PSL_SPAP_Addr;
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spap |= ((afu->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
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spap |= CXL_PSL_SPAP_V;
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pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", afu->spa, afu->spa_max_procs, afu->sw_command_status, spap);
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cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
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}
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2015-08-14 14:41:19 +07:00
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static inline void detach_spa(struct cxl_afu *afu)
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2014-10-08 15:55:02 +07:00
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{
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2014-12-08 15:18:00 +07:00
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cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
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2015-08-14 14:41:19 +07:00
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}
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void cxl_release_spa(struct cxl_afu *afu)
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{
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if (afu->spa) {
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free_pages((unsigned long) afu->spa, afu->spa_order);
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afu->spa = NULL;
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}
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2014-10-08 15:55:02 +07:00
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}
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int cxl_tlb_slb_invalidate(struct cxl *adapter)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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pr_devel("CXL adapter wide TLBIA & SLBIA\n");
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cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
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cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
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return -EBUSY;
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}
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(adapter))
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return -EIO;
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2014-10-08 15:55:02 +07:00
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cpu_relax();
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}
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cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
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return -EBUSY;
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}
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2015-08-14 14:41:18 +07:00
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if (!cxl_adapter_link_ok(adapter))
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return -EIO;
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2014-10-08 15:55:02 +07:00
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cpu_relax();
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}
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return 0;
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}
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int cxl_afu_slbia(struct cxl_afu *afu)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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pr_devel("cxl_afu_slbia issuing SLBIA command\n");
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cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
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return -EBUSY;
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}
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2015-08-14 14:41:18 +07:00
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/* If the adapter has gone down, we can assume that we
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* will PERST it and that will invalidate everything.
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*/
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if (!cxl_adapter_link_ok(afu->adapter))
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return -EIO;
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2014-10-08 15:55:02 +07:00
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cpu_relax();
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}
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return 0;
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}
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|
|
|
|
static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* 1. Disable SSTP by writing 0 to SSTP1[V] */
|
|
|
|
cxl_p2n_write(afu, CXL_SSTP1_An, 0);
|
|
|
|
|
|
|
|
/* 2. Invalidate all SLB entries */
|
|
|
|
if ((rc = cxl_afu_slbia(afu)))
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* 3. Set SSTP0_An */
|
|
|
|
cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
|
|
|
|
|
|
|
|
/* 4. Set SSTP1_An */
|
|
|
|
cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Using per slice version may improve performance here. (ie. SLBIA_An) */
|
|
|
|
static void slb_invalid(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
struct cxl *adapter = ctx->afu->adapter;
|
|
|
|
u64 slbia;
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&ctx->afu->spa_mutex));
|
|
|
|
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_LBISEL,
|
|
|
|
((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
|
|
|
|
be32_to_cpu(ctx->elem->lpid));
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
|
|
|
|
|
|
|
|
while (1) {
|
2015-08-14 14:41:18 +07:00
|
|
|
if (!cxl_adapter_link_ok(adapter))
|
|
|
|
break;
|
2014-10-08 15:55:02 +07:00
|
|
|
slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
|
|
|
|
if (!(slbia & CXL_TLB_SLB_P))
|
|
|
|
break;
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int do_process_element_cmd(struct cxl_context *ctx,
|
|
|
|
u64 cmd, u64 pe_state)
|
|
|
|
{
|
|
|
|
u64 state;
|
2014-12-08 15:17:56 +07:00
|
|
|
unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
|
2015-01-09 16:34:36 +07:00
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
trace_cxl_llcmd(ctx, cmd);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
WARN_ON(!ctx->afu->enabled);
|
|
|
|
|
|
|
|
ctx->elem->software_state = cpu_to_be32(pe_state);
|
|
|
|
smp_wmb();
|
|
|
|
*(ctx->afu->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
|
|
|
|
smp_mb();
|
|
|
|
cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
|
|
|
|
while (1) {
|
2014-12-08 15:17:56 +07:00
|
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
|
|
dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
|
2015-01-09 16:34:36 +07:00
|
|
|
rc = -EBUSY;
|
|
|
|
goto out;
|
2014-12-08 15:17:56 +07:00
|
|
|
}
|
2015-08-14 14:41:18 +07:00
|
|
|
if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
|
|
|
|
dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
|
|
|
|
rc = -EIO;
|
|
|
|
goto out;
|
|
|
|
}
|
2014-10-08 15:55:02 +07:00
|
|
|
state = be64_to_cpup(ctx->afu->sw_command_status);
|
|
|
|
if (state == ~0ULL) {
|
|
|
|
pr_err("cxl: Error adding process element to AFU\n");
|
2015-01-09 16:34:36 +07:00
|
|
|
rc = -1;
|
|
|
|
goto out;
|
2014-10-08 15:55:02 +07:00
|
|
|
}
|
|
|
|
if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
|
|
|
|
(cmd | (cmd >> 16) | ctx->pe))
|
|
|
|
break;
|
|
|
|
/*
|
|
|
|
* The command won't finish in the PSL if there are
|
|
|
|
* outstanding DSIs. Hence we need to yield here in
|
|
|
|
* case there are outstanding DSIs that we need to
|
|
|
|
* service. Tuning possiblity: we could wait for a
|
|
|
|
* while before sched
|
|
|
|
*/
|
|
|
|
schedule();
|
|
|
|
|
|
|
|
}
|
2015-01-09 16:34:36 +07:00
|
|
|
out:
|
|
|
|
trace_cxl_llcmd_done(ctx, cmd, rc);
|
|
|
|
return rc;
|
2014-10-08 15:55:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int add_process_element(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ctx->afu->spa_mutex);
|
|
|
|
pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
|
|
|
|
if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
|
|
|
|
ctx->pe_inserted = true;
|
|
|
|
pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
|
|
|
|
mutex_unlock(&ctx->afu->spa_mutex);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int terminate_process_element(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
/* fast path terminate if it's already invalid */
|
|
|
|
if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
mutex_lock(&ctx->afu->spa_mutex);
|
|
|
|
pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
|
2015-08-14 14:41:18 +07:00
|
|
|
/* We could be asked to terminate when the hw is down. That
|
|
|
|
* should always succeed: it's not running if the hw has gone
|
|
|
|
* away and is being reset.
|
|
|
|
*/
|
|
|
|
if (cxl_adapter_link_ok(ctx->afu->adapter))
|
|
|
|
rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
|
|
|
|
CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
|
2014-10-08 15:55:02 +07:00
|
|
|
ctx->elem->software_state = 0; /* Remove Valid bit */
|
|
|
|
pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
|
|
|
|
mutex_unlock(&ctx->afu->spa_mutex);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int remove_process_element(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ctx->afu->spa_mutex);
|
|
|
|
pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
|
2015-08-14 14:41:18 +07:00
|
|
|
|
|
|
|
/* We could be asked to remove when the hw is down. Again, if
|
|
|
|
* the hw is down, the PE is gone, so we succeed.
|
|
|
|
*/
|
|
|
|
if (cxl_adapter_link_ok(ctx->afu->adapter))
|
|
|
|
rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
|
|
|
|
|
|
|
|
if (!rc)
|
2014-10-08 15:55:02 +07:00
|
|
|
ctx->pe_inserted = false;
|
|
|
|
slb_invalid(ctx);
|
|
|
|
pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
|
|
|
|
mutex_unlock(&ctx->afu->spa_mutex);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2015-05-27 13:07:10 +07:00
|
|
|
void cxl_assign_psn_space(struct cxl_context *ctx)
|
2014-10-08 15:55:02 +07:00
|
|
|
{
|
|
|
|
if (!ctx->afu->pp_size || ctx->master) {
|
|
|
|
ctx->psn_phys = ctx->afu->psn_phys;
|
|
|
|
ctx->psn_size = ctx->afu->adapter->ps_size;
|
|
|
|
} else {
|
|
|
|
ctx->psn_phys = ctx->afu->psn_phys +
|
|
|
|
(ctx->afu->pp_offset + ctx->afu->pp_size * ctx->pe);
|
|
|
|
ctx->psn_size = ctx->afu->pp_size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int activate_afu_directed(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
dev_info(&afu->dev, "Activating AFU directed mode\n");
|
|
|
|
|
2015-10-07 12:07:40 +07:00
|
|
|
afu->num_procs = afu->max_procs_virtualised;
|
2015-08-14 14:41:19 +07:00
|
|
|
if (afu->spa == NULL) {
|
|
|
|
if (cxl_alloc_spa(afu))
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
attach_spa(afu);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
|
|
|
|
|
|
|
|
afu->current_mode = CXL_MODE_DIRECTED;
|
|
|
|
|
|
|
|
if ((rc = cxl_chardev_m_afu_add(afu)))
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
if ((rc = cxl_sysfs_afu_m_add(afu)))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
if ((rc = cxl_chardev_s_afu_add(afu)))
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
|
|
cxl_sysfs_afu_m_remove(afu);
|
|
|
|
err:
|
|
|
|
cxl_chardev_afu_remove(afu);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
|
|
|
#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
|
|
|
|
#else
|
|
|
|
#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
|
|
|
|
#endif
|
|
|
|
|
2015-05-27 13:07:13 +07:00
|
|
|
static u64 calculate_sr(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
u64 sr = 0;
|
|
|
|
|
|
|
|
if (ctx->master)
|
|
|
|
sr |= CXL_PSL_SR_An_MP;
|
|
|
|
if (mfspr(SPRN_LPCR) & LPCR_TC)
|
|
|
|
sr |= CXL_PSL_SR_An_TC;
|
|
|
|
if (ctx->kernel) {
|
|
|
|
sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF);
|
|
|
|
sr |= CXL_PSL_SR_An_HV;
|
|
|
|
} else {
|
|
|
|
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
|
|
|
|
set_endian(sr);
|
|
|
|
sr &= ~(CXL_PSL_SR_An_HV);
|
|
|
|
if (!test_tsk_thread_flag(current, TIF_32BIT))
|
|
|
|
sr |= CXL_PSL_SR_An_SF;
|
|
|
|
}
|
|
|
|
return sr;
|
|
|
|
}
|
|
|
|
|
2014-10-08 15:55:02 +07:00
|
|
|
static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
|
|
{
|
2015-05-27 13:07:13 +07:00
|
|
|
u32 pid;
|
2014-10-08 15:55:02 +07:00
|
|
|
int r, result;
|
|
|
|
|
2015-05-27 13:07:10 +07:00
|
|
|
cxl_assign_psn_space(ctx);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
ctx->elem->ctxtime = 0; /* disable */
|
|
|
|
ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
|
|
|
|
ctx->elem->haurp = 0; /* disable */
|
|
|
|
ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
|
|
|
|
|
2015-05-27 13:07:13 +07:00
|
|
|
pid = current->pid;
|
|
|
|
if (ctx->kernel)
|
|
|
|
pid = 0;
|
2014-10-08 15:55:02 +07:00
|
|
|
ctx->elem->common.tid = 0;
|
2015-05-27 13:07:13 +07:00
|
|
|
ctx->elem->common.pid = cpu_to_be32(pid);
|
|
|
|
|
|
|
|
ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
ctx->elem->common.csrp = 0; /* disable */
|
|
|
|
ctx->elem->common.aurp0 = 0; /* disable */
|
|
|
|
ctx->elem->common.aurp1 = 0; /* disable */
|
|
|
|
|
|
|
|
cxl_prefault(ctx, wed);
|
|
|
|
|
|
|
|
ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
|
|
|
|
ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
|
|
|
|
|
|
|
|
for (r = 0; r < CXL_IRQ_RANGES; r++) {
|
|
|
|
ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
|
|
|
|
ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->elem->common.amr = cpu_to_be64(amr);
|
|
|
|
ctx->elem->common.wed = cpu_to_be64(wed);
|
|
|
|
|
|
|
|
/* first guy needs to enable */
|
2015-05-27 13:07:10 +07:00
|
|
|
if ((result = cxl_afu_check_and_enable(ctx->afu)))
|
2014-10-08 15:55:02 +07:00
|
|
|
return result;
|
|
|
|
|
2015-07-29 11:07:22 +07:00
|
|
|
return add_process_element(ctx);
|
2014-10-08 15:55:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int deactivate_afu_directed(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
dev_info(&afu->dev, "Deactivating AFU directed mode\n");
|
|
|
|
|
|
|
|
afu->current_mode = 0;
|
|
|
|
afu->num_procs = 0;
|
|
|
|
|
|
|
|
cxl_sysfs_afu_m_remove(afu);
|
|
|
|
cxl_chardev_afu_remove(afu);
|
|
|
|
|
2015-05-27 13:07:09 +07:00
|
|
|
__cxl_afu_reset(afu);
|
2014-10-08 15:55:02 +07:00
|
|
|
cxl_afu_disable(afu);
|
|
|
|
cxl_psl_purge(afu);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int activate_dedicated_process(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
dev_info(&afu->dev, "Activating dedicated process mode\n");
|
|
|
|
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
|
|
|
|
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
|
|
|
|
cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
|
|
|
|
|
|
|
|
cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
|
|
|
|
cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
|
|
|
|
cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
|
|
|
|
|
|
|
|
afu->current_mode = CXL_MODE_DEDICATED;
|
|
|
|
afu->num_procs = 1;
|
|
|
|
|
|
|
|
return cxl_chardev_d_afu_add(afu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
|
|
{
|
|
|
|
struct cxl_afu *afu = ctx->afu;
|
2015-05-27 13:07:13 +07:00
|
|
|
u64 pid;
|
2014-10-08 15:55:02 +07:00
|
|
|
int rc;
|
|
|
|
|
2015-05-27 13:07:13 +07:00
|
|
|
pid = (u64)current->pid << 32;
|
|
|
|
if (ctx->kernel)
|
|
|
|
pid = 0;
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
|
|
|
|
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
cxl_prefault(ctx, wed);
|
|
|
|
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
|
|
|
|
(((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
|
|
|
|
(((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
|
|
|
|
(((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
|
|
|
|
((u64)ctx->irqs.offset[3] & 0xffff));
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
|
|
|
|
(((u64)ctx->irqs.range[0] & 0xffff) << 48) |
|
|
|
|
(((u64)ctx->irqs.range[1] & 0xffff) << 32) |
|
|
|
|
(((u64)ctx->irqs.range[2] & 0xffff) << 16) |
|
|
|
|
((u64)ctx->irqs.range[3] & 0xffff));
|
|
|
|
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
|
|
|
|
|
|
|
|
/* master only context for dedicated */
|
2015-05-27 13:07:10 +07:00
|
|
|
cxl_assign_psn_space(ctx);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
2015-05-27 13:07:09 +07:00
|
|
|
if ((rc = __cxl_afu_reset(afu)))
|
2014-10-08 15:55:02 +07:00
|
|
|
return rc;
|
|
|
|
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
|
|
|
|
|
|
|
|
return afu_enable(afu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int deactivate_dedicated_process(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
dev_info(&afu->dev, "Deactivating dedicated process mode\n");
|
|
|
|
|
|
|
|
afu->current_mode = 0;
|
|
|
|
afu->num_procs = 0;
|
|
|
|
|
|
|
|
cxl_chardev_afu_remove(afu);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode)
|
|
|
|
{
|
|
|
|
if (mode == CXL_MODE_DIRECTED)
|
|
|
|
return deactivate_afu_directed(afu);
|
|
|
|
if (mode == CXL_MODE_DEDICATED)
|
|
|
|
return deactivate_dedicated_process(afu);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_afu_deactivate_mode(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
return _cxl_afu_deactivate_mode(afu, afu->current_mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_afu_activate_mode(struct cxl_afu *afu, int mode)
|
|
|
|
{
|
|
|
|
if (!mode)
|
|
|
|
return 0;
|
|
|
|
if (!(mode & afu->modes_supported))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-08-14 14:41:18 +07:00
|
|
|
if (!cxl_adapter_link_ok(afu->adapter)) {
|
|
|
|
WARN(1, "Device link is down, refusing to activate!\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2014-10-08 15:55:02 +07:00
|
|
|
if (mode == CXL_MODE_DIRECTED)
|
|
|
|
return activate_afu_directed(afu);
|
|
|
|
if (mode == CXL_MODE_DEDICATED)
|
|
|
|
return activate_dedicated_process(afu);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed, u64 amr)
|
|
|
|
{
|
2015-08-14 14:41:18 +07:00
|
|
|
if (!cxl_adapter_link_ok(ctx->afu->adapter)) {
|
|
|
|
WARN(1, "Device link is down, refusing to attach process!\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2014-10-08 15:55:02 +07:00
|
|
|
ctx->kernel = kernel;
|
|
|
|
if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
|
|
|
|
return attach_afu_directed(ctx, wed, amr);
|
|
|
|
|
|
|
|
if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
|
|
|
|
return attach_dedicated(ctx, wed, amr);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int detach_process_native_dedicated(struct cxl_context *ctx)
|
|
|
|
{
|
2015-05-27 13:07:09 +07:00
|
|
|
__cxl_afu_reset(ctx->afu);
|
2014-10-08 15:55:02 +07:00
|
|
|
cxl_afu_disable(ctx->afu);
|
|
|
|
cxl_psl_purge(ctx->afu);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
if (!ctx->pe_inserted)
|
|
|
|
return 0;
|
|
|
|
if (terminate_process_element(ctx))
|
|
|
|
return -1;
|
|
|
|
if (remove_process_element(ctx))
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_detach_process(struct cxl_context *ctx)
|
|
|
|
{
|
2015-01-09 16:34:36 +07:00
|
|
|
trace_cxl_detach(ctx);
|
|
|
|
|
2014-10-08 15:55:02 +07:00
|
|
|
if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
|
|
|
|
return detach_process_native_dedicated(ctx);
|
|
|
|
|
|
|
|
return detach_process_native_afu_directed(ctx);
|
|
|
|
}
|
|
|
|
|
2014-11-14 13:37:50 +07:00
|
|
|
int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info)
|
2014-10-08 15:55:02 +07:00
|
|
|
{
|
|
|
|
u64 pidtid;
|
|
|
|
|
2015-08-14 14:41:18 +07:00
|
|
|
/* If the adapter has gone away, we can't get any meaningful
|
|
|
|
* information.
|
|
|
|
*/
|
|
|
|
if (!cxl_adapter_link_ok(afu->adapter))
|
|
|
|
return -EIO;
|
|
|
|
|
2014-11-14 13:37:50 +07:00
|
|
|
info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
|
|
|
|
info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
|
|
|
|
info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
|
|
|
|
pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
|
2014-10-08 15:55:02 +07:00
|
|
|
info->pid = pidtid >> 32;
|
|
|
|
info->tid = pidtid & 0xffffffff;
|
2014-11-14 13:37:50 +07:00
|
|
|
info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
|
|
|
|
info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
|
|
|
|
{
|
|
|
|
u64 dsisr;
|
|
|
|
|
2015-06-11 18:27:52 +07:00
|
|
|
pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
|
2014-10-08 15:55:02 +07:00
|
|
|
|
|
|
|
/* Clear PSL_DSISR[PE] */
|
|
|
|
dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
|
|
|
|
|
|
|
|
/* Write 1s to clear error status bits */
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
|
|
|
|
{
|
2015-01-09 16:34:36 +07:00
|
|
|
trace_cxl_psl_irq_ack(ctx, tfc);
|
2014-10-08 15:55:02 +07:00
|
|
|
if (tfc)
|
|
|
|
cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
|
|
|
|
if (psl_reset_mask)
|
|
|
|
recover_psl_err(ctx->afu, psl_reset_mask);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_check_error(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
|
|
|
|
}
|