2015-10-07 22:36:28 +07:00
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#
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# FPGA framework configuration
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#
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menu "FPGA Configuration Support"
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config FPGA
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tristate "FPGA Configuration Framework"
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help
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Say Y here if you want support for configuring FPGAs from the
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kernel. The FPGA framework adds a FPGA manager class and FPGA
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manager drivers.
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2015-10-07 22:36:29 +07:00
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if FPGA
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2016-11-02 02:14:29 +07:00
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config FPGA_REGION
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tristate "FPGA Region"
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depends on OF && FPGA_BRIDGE
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help
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FPGA Regions allow loading FPGA images under control of
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the Device Tree.
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2015-10-07 22:36:29 +07:00
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config FPGA_MGR_SOCFPGA
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tristate "Altera SOCFPGA FPGA Manager"
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2016-11-22 05:26:42 +07:00
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depends on ARCH_SOCFPGA || COMPILE_TEST
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2015-10-07 22:36:29 +07:00
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help
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FPGA manager driver support for Altera SOCFPGA.
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2016-11-02 02:14:32 +07:00
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config FPGA_MGR_SOCFPGA_A10
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tristate "Altera SoCFPGA Arria10"
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2016-11-22 05:26:42 +07:00
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depends on ARCH_SOCFPGA || COMPILE_TEST
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select REGMAP_MMIO
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2016-11-02 02:14:32 +07:00
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help
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FPGA manager driver support for Altera Arria10 SoCFPGA.
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2015-10-17 05:42:30 +07:00
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config FPGA_MGR_ZYNQ_FPGA
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tristate "Xilinx Zynq FPGA"
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2016-09-08 21:38:05 +07:00
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depends on ARCH_ZYNQ || COMPILE_TEST
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2016-08-04 03:45:46 +07:00
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depends on HAS_DMA
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2015-10-17 05:42:30 +07:00
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help
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FPGA manager driver support for Xilinx Zynq FPGAs.
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2016-11-02 02:14:28 +07:00
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config FPGA_BRIDGE
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tristate "FPGA Bridge Framework"
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depends on OF
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help
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Say Y here if you want to support bridges connected between host
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processors and FPGAs or between FPGAs.
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2016-11-02 02:14:30 +07:00
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config SOCFPGA_FPGA_BRIDGE
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tristate "Altera SoCFPGA FPGA Bridges"
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depends on ARCH_SOCFPGA && FPGA_BRIDGE
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help
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Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
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devices.
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2016-11-02 02:14:31 +07:00
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config ALTERA_FREEZE_BRIDGE
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tristate "Altera FPGA Freeze Bridge"
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depends on ARCH_SOCFPGA && FPGA_BRIDGE
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help
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Say Y to enable drivers for Altera FPGA Freeze bridges. A
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freeze bridge is a bridge that exists in the FPGA fabric to
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isolate one region of the FPGA from the busses while that
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region is being reprogrammed.
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2015-10-07 22:36:29 +07:00
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endif # FPGA
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2015-10-07 22:36:28 +07:00
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endmenu
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