2018-09-05 13:25:12 +07:00
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-contiguous.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/genalloc.h>
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#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/scatterlist.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#include <asm/cache.h>
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static inline void cache_op(phys_addr_t paddr, size_t size,
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void (*fn)(unsigned long start, unsigned long end))
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{
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2019-07-30 16:02:26 +07:00
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struct page *page = phys_to_page(paddr);
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void *start = __va(page_to_phys(page));
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unsigned long offset = offset_in_page(paddr);
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size_t left = size;
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2018-09-05 13:25:12 +07:00
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do {
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size_t len = left;
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2019-07-30 16:02:26 +07:00
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if (offset + len > PAGE_SIZE)
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len = PAGE_SIZE - offset;
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2018-09-05 13:25:12 +07:00
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if (PageHighMem(page)) {
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2019-07-30 16:02:26 +07:00
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start = kmap_atomic(page);
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2018-09-05 13:25:12 +07:00
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2019-07-30 16:02:26 +07:00
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fn((unsigned long)start + offset,
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(unsigned long)start + offset + len);
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2018-09-05 13:25:12 +07:00
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2019-07-30 16:02:26 +07:00
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kunmap_atomic(start);
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2018-09-05 13:25:12 +07:00
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} else {
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2019-07-30 16:02:26 +07:00
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fn((unsigned long)start + offset,
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(unsigned long)start + offset + len);
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2018-09-05 13:25:12 +07:00
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}
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offset = 0;
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2019-07-30 16:02:26 +07:00
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2018-09-05 13:25:12 +07:00
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page++;
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2019-07-30 16:02:26 +07:00
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start += PAGE_SIZE;
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2018-09-05 13:25:12 +07:00
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left -= len;
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} while (left);
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}
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2019-07-30 16:02:26 +07:00
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static void dma_wbinv_set_zero_range(unsigned long start, unsigned long end)
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{
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memset((void *)start, 0, end - start);
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dma_wbinv_range(start, end);
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}
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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cache_op(page_to_phys(page), size, dma_wbinv_set_zero_range);
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}
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2019-11-08 00:03:11 +07:00
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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2018-09-05 13:25:12 +07:00
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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cache_op(paddr, size, dma_wb_range);
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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cache_op(paddr, size, dma_wbinv_range);
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break;
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default:
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BUG();
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}
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}
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2019-11-08 00:03:11 +07:00
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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2018-09-05 13:25:12 +07:00
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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2019-07-30 16:16:28 +07:00
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return;
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2018-09-05 13:25:12 +07:00
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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2019-07-30 16:16:28 +07:00
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cache_op(paddr, size, dma_inv_range);
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2018-09-05 13:25:12 +07:00
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break;
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default:
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BUG();
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}
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}
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