mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Freescale SAI BCLK as a generic clock driver
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*
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* Copyright 2020 Michael Walle <michael@walle.cc>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#define I2S_CSR 0x00
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#define I2S_CR2 0x08
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#define CSR_BCE_BIT 28
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#define CR2_BCD BIT(24)
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#define CR2_DIV_SHIFT 0
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#define CR2_DIV_WIDTH 8
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struct fsl_sai_clk {
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struct clk_divider div;
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struct clk_gate gate;
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spinlock_t lock;
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};
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static int fsl_sai_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct fsl_sai_clk *sai_clk;
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struct clk_parent_data pdata = { .index = 0 };
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void __iomem *base;
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struct clk_hw *hw;
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struct resource *res;
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sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
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if (!sai_clk)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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spin_lock_init(&sai_clk->lock);
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sai_clk->gate.reg = base + I2S_CSR;
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sai_clk->gate.bit_idx = CSR_BCE_BIT;
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sai_clk->gate.lock = &sai_clk->lock;
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sai_clk->div.reg = base + I2S_CR2;
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sai_clk->div.shift = CR2_DIV_SHIFT;
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sai_clk->div.width = CR2_DIV_WIDTH;
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sai_clk->div.lock = &sai_clk->lock;
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/* set clock direction, we are the BCLK master */
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writel(CR2_BCD, base + I2S_CR2);
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hw = clk_hw_register_composite_pdata(dev, dev->of_node->name,
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&pdata, 1, NULL, NULL,
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&sai_clk->div.hw,
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&clk_divider_ops,
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&sai_clk->gate.hw,
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&clk_gate_ops,
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CLK_SET_RATE_GATE);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
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}
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static const struct of_device_id of_fsl_sai_clk_ids[] = {
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{ .compatible = "fsl,vf610-sai-clock" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
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static struct platform_driver fsl_sai_clk_driver = {
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.probe = fsl_sai_clk_probe,
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.driver = {
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.name = "fsl-sai-clk",
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.of_match_table = of_fsl_sai_clk_ids,
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},
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};
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module_platform_driver(fsl_sai_clk_driver);
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MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
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MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:fsl-sai-clk");
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