2006-03-29 03:00:40 +07:00
|
|
|
/*
|
|
|
|
* linux/arch/arm/mm/proc-xsc3.S
|
|
|
|
*
|
|
|
|
* Original Author: Matthew Gilbert
|
2006-12-20 03:48:15 +07:00
|
|
|
* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
|
|
|
* Copyright 2004 (C) Intel Corp.
|
2007-02-05 06:55:27 +07:00
|
|
|
* Copyright 2005 (C) MontaVista Software, Inc.
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*
|
2007-02-05 06:55:27 +07:00
|
|
|
* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
|
|
|
|
* an extension to Intel's original XScale core that adds the following
|
2006-03-29 03:00:40 +07:00
|
|
|
* features:
|
|
|
|
*
|
|
|
|
* - ARMv6 Supersections
|
|
|
|
* - Low Locality Reference pages (replaces mini-cache)
|
|
|
|
* - 36-bit addressing
|
|
|
|
* - L2 cache
|
2007-02-05 06:55:27 +07:00
|
|
|
* - Cache coherency if chipset supports it
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
2007-02-05 06:55:27 +07:00
|
|
|
* Based on original XScale code by Nicolas Pitre.
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/linkage.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <asm/assembler.h>
|
2008-09-08 01:15:31 +07:00
|
|
|
#include <asm/hwcap.h>
|
2006-03-29 03:00:40 +07:00
|
|
|
#include <asm/pgtable.h>
|
2006-03-30 16:24:07 +07:00
|
|
|
#include <asm/pgtable-hwdef.h>
|
2006-03-29 03:00:40 +07:00
|
|
|
#include <asm/page.h>
|
|
|
|
#include <asm/ptrace.h>
|
|
|
|
#include "proc-macros.S"
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is the maximum size of an area which will be flushed. If the
|
|
|
|
* area is larger than this, then we flush the whole cache.
|
|
|
|
*/
|
|
|
|
#define MAX_AREA_SIZE 32768
|
|
|
|
|
|
|
|
/*
|
2007-02-05 06:55:27 +07:00
|
|
|
* The cache line size of the L1 I, L1 D and unified L2 cache.
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
|
|
|
#define CACHELINESIZE 32
|
|
|
|
|
|
|
|
/*
|
2007-02-05 06:55:27 +07:00
|
|
|
* The size of the L1 D cache.
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
|
|
|
#define CACHESIZE 32768
|
|
|
|
|
|
|
|
/*
|
2007-02-05 06:55:27 +07:00
|
|
|
* This macro is used to wait for a CP15 write and is needed when we
|
|
|
|
* have to ensure that the last operation to the coprocessor was
|
|
|
|
* completed before continuing with operation.
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
|
|
|
.macro cpwait_ret, lr, rd
|
|
|
|
mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
|
|
|
|
sub pc, \lr, \rd, LSR #32 @ wait for completion and
|
|
|
|
@ flush instruction pipeline
|
|
|
|
.endm
|
|
|
|
|
|
|
|
/*
|
2007-02-05 06:55:27 +07:00
|
|
|
* This macro cleans and invalidates the entire L1 D cache.
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
.macro clean_d_cache rd, rs
|
|
|
|
mov \rd, #0x1f00
|
|
|
|
orr \rd, \rd, #0x00e0
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
adds \rd, \rd, #0x40000000
|
|
|
|
bcc 1b
|
|
|
|
subs \rd, \rd, #0x20
|
|
|
|
bpl 1b
|
|
|
|
.endm
|
|
|
|
|
|
|
|
.text
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_xsc3_proc_init()
|
|
|
|
*
|
|
|
|
* Nothing too exciting at the moment
|
|
|
|
*/
|
|
|
|
ENTRY(cpu_xsc3_proc_init)
|
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_xsc3_proc_fin()
|
|
|
|
*/
|
|
|
|
ENTRY(cpu_xsc3_proc_fin)
|
|
|
|
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
|
|
|
|
bic r0, r0, #0x1800 @ ...IZ...........
|
|
|
|
bic r0, r0, #0x0006 @ .............CA.
|
|
|
|
mcr p15, 0, r0, c1, c0, 0 @ disable caches
|
2010-07-26 18:22:12 +07:00
|
|
|
mov pc, lr
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_xsc3_reset(loc)
|
|
|
|
*
|
|
|
|
* Perform a soft reset of the system. Put the CPU into the
|
|
|
|
* same state as it would be if it had been reset, and branch
|
|
|
|
* to what would be the reset vector.
|
|
|
|
*
|
|
|
|
* loc: location to jump to for soft reset
|
|
|
|
*/
|
|
|
|
.align 5
|
2011-11-15 20:25:04 +07:00
|
|
|
.pushsection .idmap.text, "ax"
|
2006-03-29 03:00:40 +07:00
|
|
|
ENTRY(cpu_xsc3_reset)
|
|
|
|
mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
|
|
|
|
msr cpsr_c, r1 @ reset CPSR
|
|
|
|
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
|
|
|
|
bic r1, r1, #0x3900 @ ..VIZ..S........
|
2007-02-05 06:55:27 +07:00
|
|
|
bic r1, r1, #0x0086 @ ........B....CA.
|
2006-03-29 03:00:40 +07:00
|
|
|
mcr p15, 0, r1, c1, c0, 0 @ ctrl register
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
|
2006-03-29 03:00:40 +07:00
|
|
|
bic r1, r1, #0x0001 @ ...............M
|
|
|
|
mcr p15, 0, r1, c1, c0, 0 @ ctrl register
|
|
|
|
@ CAUTION: MMU turned off from this point. We count on the pipeline
|
|
|
|
@ already containing those two last instructions to survive.
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, r0
|
2011-11-15 20:25:04 +07:00
|
|
|
ENDPROC(cpu_xsc3_reset)
|
|
|
|
.popsection
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_xsc3_do_idle()
|
|
|
|
*
|
|
|
|
* Cause the processor to idle
|
|
|
|
*
|
|
|
|
* For now we do nothing but go to idle mode for every case
|
|
|
|
*
|
|
|
|
* XScale supports clock switching, but using idle mode support
|
|
|
|
* allows external hardware to react to system state changes.
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
|
|
|
|
ENTRY(cpu_xsc3_do_idle)
|
|
|
|
mov r0, #1
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p14, 0, r0, c7, c0, 0 @ go to idle
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/* ================================= CACHE ================================ */
|
|
|
|
|
2010-10-28 17:27:40 +07:00
|
|
|
/*
|
|
|
|
* flush_icache_all()
|
|
|
|
*
|
|
|
|
* Unconditionally clean and invalidate the entire icache.
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_flush_icache_all)
|
|
|
|
mov r0, #0
|
|
|
|
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
|
|
|
mov pc, lr
|
|
|
|
ENDPROC(xsc3_flush_icache_all)
|
|
|
|
|
2006-03-29 03:00:40 +07:00
|
|
|
/*
|
|
|
|
* flush_user_cache_all()
|
|
|
|
*
|
|
|
|
* Invalidate all cache entries in a particular address
|
|
|
|
* space.
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_flush_user_cache_all)
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* flush_kern_cache_all()
|
|
|
|
*
|
|
|
|
* Clean and invalidate the entire cache.
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_flush_kern_cache_all)
|
|
|
|
mov r2, #VM_EXEC
|
|
|
|
mov ip, #0
|
|
|
|
__flush_whole_cache:
|
|
|
|
clean_d_cache r0, r1
|
|
|
|
tst r2, #VM_EXEC
|
2007-02-05 06:55:27 +07:00
|
|
|
mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
|
|
|
|
mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
|
|
|
|
mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* flush_user_cache_range(start, end, vm_flags)
|
|
|
|
*
|
|
|
|
* Invalidate a range of cache entries in the specified
|
|
|
|
* address space.
|
|
|
|
*
|
|
|
|
* - start - start address (may not be aligned)
|
|
|
|
* - end - end address (exclusive, may not be aligned)
|
|
|
|
* - vma - vma_area_struct describing address space
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
ENTRY(xsc3_flush_user_cache_range)
|
|
|
|
mov ip, #0
|
|
|
|
sub r3, r1, r0 @ calculate total size
|
|
|
|
cmp r3, #MAX_AREA_SIZE
|
|
|
|
bhs __flush_whole_cache
|
|
|
|
|
|
|
|
1: tst r2, #VM_EXEC
|
2007-02-05 06:55:27 +07:00
|
|
|
mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
|
|
|
|
mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
|
|
|
tst r2, #VM_EXEC
|
2007-02-05 06:55:27 +07:00
|
|
|
mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
|
|
|
|
mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
|
|
|
|
mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* coherent_kern_range(start, end)
|
|
|
|
*
|
2007-02-05 06:55:27 +07:00
|
|
|
* Ensure coherency between the I cache and the D cache in the
|
2006-03-29 03:00:40 +07:00
|
|
|
* region described by start. If you have non-snooping
|
|
|
|
* Harvard caches, you need to implement this function.
|
|
|
|
*
|
|
|
|
* - start - virtual start address
|
|
|
|
* - end - virtual end address
|
|
|
|
*
|
|
|
|
* Note: single I-cache line invalidation isn't used here since
|
|
|
|
* it also trashes the mini I-cache used by JTAG debuggers.
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_coherent_kern_range)
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
ENTRY(xsc3_coherent_user_range)
|
|
|
|
bic r0, r0, #CACHELINESIZE - 1
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
|
|
|
mov r0, #0
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
|
|
|
|
mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
2009-11-26 19:56:21 +07:00
|
|
|
* flush_kern_dcache_area(void *addr, size_t size)
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
|
|
|
* Ensure no D cache aliasing occurs, either with itself or
|
2007-02-05 06:55:27 +07:00
|
|
|
* the I cache.
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
2009-11-26 19:56:21 +07:00
|
|
|
* - addr - kernel address
|
|
|
|
* - size - region size
|
2006-03-29 03:00:40 +07:00
|
|
|
*/
|
2009-11-26 19:56:21 +07:00
|
|
|
ENTRY(xsc3_flush_kern_dcache_area)
|
|
|
|
add r1, r0, r1
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
|
|
|
mov r0, #0
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
|
|
|
|
mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* dma_inv_range(start, end)
|
|
|
|
*
|
|
|
|
* Invalidate (discard) the specified virtual address range.
|
|
|
|
* May not write back any entries. If 'start' or 'end'
|
|
|
|
* are not cache line aligned, those lines must be written
|
|
|
|
* back.
|
|
|
|
*
|
|
|
|
* - start - virtual start address
|
|
|
|
* - end - virtual end address
|
|
|
|
*/
|
2009-11-26 23:24:19 +07:00
|
|
|
xsc3_dma_inv_range:
|
2006-03-29 03:00:40 +07:00
|
|
|
tst r0, #CACHELINESIZE - 1
|
|
|
|
bic r0, r0, #CACHELINESIZE - 1
|
2007-02-05 06:55:27 +07:00
|
|
|
mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
tst r1, #CACHELINESIZE - 1
|
2007-02-05 06:55:27 +07:00
|
|
|
mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
|
|
|
|
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* dma_clean_range(start, end)
|
|
|
|
*
|
|
|
|
* Clean the specified virtual address range.
|
|
|
|
*
|
|
|
|
* - start - virtual start address
|
|
|
|
* - end - virtual end address
|
|
|
|
*/
|
2009-11-26 23:24:19 +07:00
|
|
|
xsc3_dma_clean_range:
|
2006-03-29 03:00:40 +07:00
|
|
|
bic r0, r0, #CACHELINESIZE - 1
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* dma_flush_range(start, end)
|
|
|
|
*
|
|
|
|
* Clean and invalidate the specified virtual address range.
|
|
|
|
*
|
|
|
|
* - start - virtual start address
|
|
|
|
* - end - virtual end address
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_dma_flush_range)
|
|
|
|
bic r0, r0, #CACHELINESIZE - 1
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
cmp r0, r1
|
|
|
|
blo 1b
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
2009-11-26 23:19:58 +07:00
|
|
|
/*
|
|
|
|
* dma_map_area(start, size, dir)
|
|
|
|
* - start - kernel virtual start address
|
|
|
|
* - size - size of region
|
|
|
|
* - dir - DMA direction
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_dma_map_area)
|
|
|
|
add r1, r1, r0
|
|
|
|
cmp r2, #DMA_TO_DEVICE
|
|
|
|
beq xsc3_dma_clean_range
|
|
|
|
bcs xsc3_dma_inv_range
|
|
|
|
b xsc3_dma_flush_range
|
|
|
|
ENDPROC(xsc3_dma_map_area)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* dma_unmap_area(start, size, dir)
|
|
|
|
* - start - kernel virtual start address
|
|
|
|
* - size - size of region
|
|
|
|
* - dir - DMA direction
|
|
|
|
*/
|
|
|
|
ENTRY(xsc3_dma_unmap_area)
|
|
|
|
mov pc, lr
|
|
|
|
ENDPROC(xsc3_dma_unmap_area)
|
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
|
|
|
|
define_cache_functions xsc3
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
ENTRY(cpu_xsc3_dcache_clean_area)
|
2007-02-05 06:55:27 +07:00
|
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
|
2006-03-29 03:00:40 +07:00
|
|
|
add r0, r0, #CACHELINESIZE
|
|
|
|
subs r1, r1, #CACHELINESIZE
|
|
|
|
bhi 1b
|
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
/* =============================== PageTable ============================== */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* cpu_xsc3_switch_mm(pgd)
|
|
|
|
*
|
|
|
|
* Set the translation base pointer to be as described by pgd.
|
|
|
|
*
|
|
|
|
* pgd: new page tables
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
ENTRY(cpu_xsc3_switch_mm)
|
|
|
|
clean_d_cache r1, r2
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ data write barrier
|
|
|
|
mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
|
2006-03-29 03:00:40 +07:00
|
|
|
orr r0, r0, #0x18 @ cache the page table in L2
|
|
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
|
2006-03-29 03:00:40 +07:00
|
|
|
cpwait_ret lr, ip
|
|
|
|
|
|
|
|
/*
|
2006-12-13 21:34:43 +07:00
|
|
|
* cpu_xsc3_set_pte_ext(ptep, pte, ext)
|
2006-03-29 03:00:40 +07:00
|
|
|
*
|
|
|
|
* Set a PTE and flush it out
|
|
|
|
*/
|
2008-09-07 02:47:54 +07:00
|
|
|
cpu_xsc3_mt_table:
|
|
|
|
.long 0x00 @ L_PTE_MT_UNCACHED
|
2008-09-07 18:36:46 +07:00
|
|
|
.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
|
2008-10-25 00:21:45 +07:00
|
|
|
.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
|
2008-09-07 18:36:46 +07:00
|
|
|
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
|
|
|
|
.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
|
2008-09-07 03:07:45 +07:00
|
|
|
.long 0x00 @ unused
|
2008-09-07 02:47:54 +07:00
|
|
|
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
|
|
|
|
.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
|
2008-09-07 03:07:45 +07:00
|
|
|
.long 0x00 @ unused
|
2008-09-07 02:47:54 +07:00
|
|
|
.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
|
|
|
|
.long 0x00 @ unused
|
2008-09-07 18:36:46 +07:00
|
|
|
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
|
|
|
|
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
|
2008-09-07 18:42:51 +07:00
|
|
|
.long 0x00 @ unused
|
2008-09-07 02:47:54 +07:00
|
|
|
.long 0x00 @ unused
|
|
|
|
.long 0x00 @ unused
|
|
|
|
|
2006-03-29 03:00:40 +07:00
|
|
|
.align 5
|
2006-12-13 21:34:43 +07:00
|
|
|
ENTRY(cpu_xsc3_set_pte_ext)
|
2008-09-06 23:19:08 +07:00
|
|
|
xscale_set_pte_ext_prologue
|
2006-03-29 03:00:40 +07:00
|
|
|
|
2008-09-06 23:19:08 +07:00
|
|
|
tst r1, #L_PTE_SHARED @ shared?
|
2008-09-07 02:47:54 +07:00
|
|
|
and r1, r1, #L_PTE_MT_MASK
|
|
|
|
adr ip, cpu_xsc3_mt_table
|
|
|
|
ldr ip, [ip, r1]
|
|
|
|
orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
|
|
|
|
bic r2, r2, #0x0c @ clear old C,B bits
|
|
|
|
orr r2, r2, ip
|
2006-03-29 03:00:40 +07:00
|
|
|
|
2008-09-06 23:19:08 +07:00
|
|
|
xscale_set_pte_ext_epilogue
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
.ltorg
|
|
|
|
.align
|
|
|
|
|
2011-02-06 22:48:39 +07:00
|
|
|
.globl cpu_xsc3_suspend_size
|
2011-08-28 04:39:09 +07:00
|
|
|
.equ cpu_xsc3_suspend_size, 4 * 6
|
2011-04-02 16:08:55 +07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2011-02-06 22:48:39 +07:00
|
|
|
ENTRY(cpu_xsc3_do_suspend)
|
2011-08-28 04:39:09 +07:00
|
|
|
stmfd sp!, {r4 - r9, lr}
|
2011-02-06 22:48:39 +07:00
|
|
|
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
|
|
|
|
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
|
|
|
mrc p15, 0, r6, c13, c0, 0 @ PID
|
|
|
|
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
2011-08-28 04:39:09 +07:00
|
|
|
mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
|
|
|
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
2011-02-06 22:48:39 +07:00
|
|
|
bic r4, r4, #2 @ clear frequency change bit
|
2011-08-28 04:39:09 +07:00
|
|
|
stmia r0, {r4 - r9} @ store cp regs
|
|
|
|
ldmia sp!, {r4 - r9, pc}
|
2011-02-06 22:48:39 +07:00
|
|
|
ENDPROC(cpu_xsc3_do_suspend)
|
|
|
|
|
|
|
|
ENTRY(cpu_xsc3_do_resume)
|
2011-08-28 04:39:09 +07:00
|
|
|
ldmia r0, {r4 - r9} @ load cp regs
|
2011-02-06 22:48:39 +07:00
|
|
|
mov ip, #0
|
|
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
|
|
|
|
mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
|
|
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
|
|
|
mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
|
|
|
|
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
|
|
|
mcr p15, 0, r6, c13, c0, 0 @ PID
|
|
|
|
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
2011-08-28 04:39:09 +07:00
|
|
|
orr r1, r1, #0x18 @ cache the page table in L2
|
|
|
|
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
|
|
|
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
|
|
|
mov r0, r9 @ control register
|
2011-02-06 22:48:39 +07:00
|
|
|
b cpu_resume_mmu
|
|
|
|
ENDPROC(cpu_xsc3_do_resume)
|
|
|
|
#endif
|
|
|
|
|
2010-10-01 21:37:05 +07:00
|
|
|
__CPUINIT
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
.type __xsc3_setup, #function
|
|
|
|
__xsc3_setup:
|
|
|
|
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
|
|
|
|
msr cpsr_c, r0
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ data write barrier
|
|
|
|
mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
|
|
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
|
2006-03-29 03:00:40 +07:00
|
|
|
orr r4, r4, #0x18 @ cache the page table in L2
|
|
|
|
mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
|
2007-02-05 06:55:27 +07:00
|
|
|
|
2009-10-30 01:46:56 +07:00
|
|
|
mov r0, #1 << 6 @ cp6 access for early sched_clock
|
2007-02-05 06:55:27 +07:00
|
|
|
mcr p15, 0, r0, c15, c1, 0 @ write CP access register
|
|
|
|
|
2006-03-29 03:00:40 +07:00
|
|
|
mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
|
|
|
|
and r0, r0, #2 @ preserve bit P bit setting
|
|
|
|
orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
|
|
|
|
mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
|
2006-06-29 21:09:57 +07:00
|
|
|
|
|
|
|
adr r5, xsc3_crval
|
|
|
|
ldmia r5, {r5, r6}
|
2009-12-30 22:02:57 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_CACHE_XSC3L2
|
|
|
|
mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
|
|
|
|
ands r0, r0, #0xf8
|
|
|
|
orrne r6, r6, #(1 << 26) @ enable L2 if present
|
|
|
|
#endif
|
|
|
|
|
2006-03-29 03:00:40 +07:00
|
|
|
mrc p15, 0, r0, c1, c0, 0 @ get control register
|
2007-02-05 06:55:27 +07:00
|
|
|
bic r0, r0, r5 @ ..V. ..R. .... ..A.
|
|
|
|
orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
|
|
|
|
@ ...I Z..S .... .... (uc)
|
2006-03-29 03:00:40 +07:00
|
|
|
mov pc, lr
|
|
|
|
|
|
|
|
.size __xsc3_setup, . - __xsc3_setup
|
|
|
|
|
2006-06-29 21:09:57 +07:00
|
|
|
.type xsc3_crval, #object
|
|
|
|
xsc3_crval:
|
2007-02-05 06:55:27 +07:00
|
|
|
crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
|
2006-06-29 21:09:57 +07:00
|
|
|
|
2006-03-29 03:00:40 +07:00
|
|
|
__INITDATA
|
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
|
|
define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
.section ".rodata"
|
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
string cpu_arch_name, "armv5te"
|
|
|
|
string cpu_elf_name, "v5"
|
|
|
|
string cpu_xsc3_name, "XScale-V3 based processor"
|
2006-03-29 03:00:40 +07:00
|
|
|
|
|
|
|
.align
|
|
|
|
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
|
|
|
|
.type __\name\()_proc_info,#object
|
|
|
|
__\name\()_proc_info:
|
|
|
|
.long \cpu_val
|
|
|
|
.long \cpu_mask
|
2006-06-30 00:24:21 +07:00
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_BUFFERABLE | \
|
|
|
|
PMD_SECT_CACHEABLE | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
2007-02-05 06:55:27 +07:00
|
|
|
.long PMD_TYPE_SECT | \
|
2006-06-30 00:24:21 +07:00
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
2006-03-29 03:00:40 +07:00
|
|
|
b __xsc3_setup
|
|
|
|
.long cpu_arch_name
|
|
|
|
.long cpu_elf_name
|
|
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
|
|
.long cpu_xsc3_name
|
|
|
|
.long xsc3_processor_functions
|
|
|
|
.long v4wbi_tlb_fns
|
|
|
|
.long xsc3_mc_user_fns
|
|
|
|
.long xsc3_cache_fns
|
2011-06-23 23:26:38 +07:00
|
|
|
.size __\name\()_proc_info, . - __\name\()_proc_info
|
|
|
|
.endm
|
2008-11-29 20:42:39 +07:00
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
xsc3_proc_info xsc3, 0x69056000, 0xffffe000
|
2008-11-29 20:42:39 +07:00
|
|
|
|
2011-06-23 23:26:38 +07:00
|
|
|
/* Note: PXA935 changed its implementor ID from Intel to Marvell */
|
|
|
|
xsc3_proc_info xsc3_pxa935, 0x56056000, 0xffffe000
|