ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
Ideally it should be initialized by the boot loader, but it isn't.
For the boot CPU, CNTVOFF is initialized by Linux since commit
9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
initialization for r8a7794").
For secondary CPU cores, no such initialization is done.
Hence when enabling SMP on r8a7794, the kernel log is spammed with:
WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
Please report this, consider using a different clocksource, if possible.
Your kernel is probably still fine.
As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
respect to CNTVOFF, we have been very lucky this just worked on R-Car
Gen2 SoCs with Cortex-A15 cores.
To fix this:
- Move the existing inline asm code to initialize CNTVOFF to an
assembler source file (adding comments and replacing hardcoded
constants by definitions in the process), so it can be reused,
- Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
- Wrap the standard secondary_startup() routine inside a routine which
initializes CNTVOFF.
Based on patches by Hisashi Nakamura in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-01 15:37:45 +07:00
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/*
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* SMP support for APMU based systems with Cortex A7/A15
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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ENTRY(shmobile_init_cntvoff)
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/*
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* CNTVOFF has to be initialized either from non-secure Hypervisor
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* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
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* then it should be handled by the secure code
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*/
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cps #MON_MODE
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mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
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orr r0, r1, #1
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mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
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instr_sync
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mov r0, #0
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mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
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instr_sync
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mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
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instr_sync
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cps #SVC_MODE
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ret lr
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ENDPROC(shmobile_init_cntvoff)
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2017-10-05 19:09:04 +07:00
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#ifdef CONFIG_SMP
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ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
Ideally it should be initialized by the boot loader, but it isn't.
For the boot CPU, CNTVOFF is initialized by Linux since commit
9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
initialization for r8a7794").
For secondary CPU cores, no such initialization is done.
Hence when enabling SMP on r8a7794, the kernel log is spammed with:
WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
Please report this, consider using a different clocksource, if possible.
Your kernel is probably still fine.
As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
respect to CNTVOFF, we have been very lucky this just worked on R-Car
Gen2 SoCs with Cortex-A15 cores.
To fix this:
- Move the existing inline asm code to initialize CNTVOFF to an
assembler source file (adding comments and replacing hardcoded
constants by definitions in the process), so it can be reused,
- Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
- Wrap the standard secondary_startup() routine inside a routine which
initializes CNTVOFF.
Based on patches by Hisashi Nakamura in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-01 15:37:45 +07:00
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ENTRY(shmobile_boot_apmu)
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bl shmobile_init_cntvoff
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b secondary_startup
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ENDPROC(shmobile_boot_apmu)
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2017-10-05 19:09:04 +07:00
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#endif
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