2006-02-10 13:05:54 +07:00
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/* pci_sun4v.h: SUN4V specific PCI controller support.
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*
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* Copyright (C) 2006 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _PCI_SUN4V_H
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#define _PCI_SUN4V_H
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2014-05-17 04:25:51 +07:00
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long pci_sun4v_iommu_map(unsigned long devhandle,
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unsigned long tsbid,
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unsigned long num_ttes,
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unsigned long io_attributes,
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unsigned long io_page_list_pa);
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unsigned long pci_sun4v_iommu_demap(unsigned long devhandle,
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unsigned long tsbid,
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unsigned long num_ttes);
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unsigned long pci_sun4v_iommu_getmap(unsigned long devhandle,
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unsigned long tsbid,
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unsigned long *io_attributes,
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unsigned long *real_address);
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unsigned long pci_sun4v_config_get(unsigned long devhandle,
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unsigned long pci_device,
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unsigned long config_offset,
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unsigned long size);
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int pci_sun4v_config_put(unsigned long devhandle,
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unsigned long pci_device,
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unsigned long config_offset,
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unsigned long size,
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unsigned long data);
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2006-02-10 13:05:54 +07:00
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2014-05-17 04:25:51 +07:00
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unsigned long pci_sun4v_msiq_conf(unsigned long devhandle,
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[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 08:41:02 +07:00
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unsigned long msiqid,
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unsigned long msiq_paddr,
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unsigned long num_entries);
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2014-05-17 04:25:51 +07:00
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unsigned long pci_sun4v_msiq_info(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long *msiq_paddr,
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unsigned long *num_entries);
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unsigned long pci_sun4v_msiq_getvalid(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long *valid);
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unsigned long pci_sun4v_msiq_setvalid(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long valid);
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unsigned long pci_sun4v_msiq_getstate(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long *state);
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unsigned long pci_sun4v_msiq_setstate(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long state);
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unsigned long pci_sun4v_msiq_gethead(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long *head);
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unsigned long pci_sun4v_msiq_sethead(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long head);
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unsigned long pci_sun4v_msiq_gettail(unsigned long devhandle,
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unsigned long msiqid,
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unsigned long *head);
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unsigned long pci_sun4v_msi_getvalid(unsigned long devhandle,
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unsigned long msinum,
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unsigned long *valid);
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unsigned long pci_sun4v_msi_setvalid(unsigned long devhandle,
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unsigned long msinum,
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unsigned long valid);
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unsigned long pci_sun4v_msi_getmsiq(unsigned long devhandle,
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unsigned long msinum,
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unsigned long *msiq);
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unsigned long pci_sun4v_msi_setmsiq(unsigned long devhandle,
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unsigned long msinum,
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unsigned long msiq,
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unsigned long msitype);
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unsigned long pci_sun4v_msi_getstate(unsigned long devhandle,
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unsigned long msinum,
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unsigned long *state);
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unsigned long pci_sun4v_msi_setstate(unsigned long devhandle,
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unsigned long msinum,
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unsigned long state);
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unsigned long pci_sun4v_msg_getmsiq(unsigned long devhandle,
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unsigned long msinum,
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unsigned long *msiq);
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unsigned long pci_sun4v_msg_setmsiq(unsigned long devhandle,
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unsigned long msinum,
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unsigned long msiq);
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unsigned long pci_sun4v_msg_getvalid(unsigned long devhandle,
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unsigned long msinum,
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unsigned long *valid);
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unsigned long pci_sun4v_msg_setvalid(unsigned long devhandle,
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unsigned long msinum,
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unsigned long valid);
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[SPARC64]: Add PCI MSI support on Niagara.
This is kind of hokey, we could use the hardware provided facilities
much better.
MSIs are assosciated with MSI Queues. MSI Queues generate interrupts
when any MSI assosciated with it is signalled. This suggests a
two-tiered IRQ dispatch scheme:
MSI Queue interrupt --> queue interrupt handler
MSI dispatch --> driver interrupt handler
But we just get one-level under Linux currently. What I'd like to do
is possibly stick the IRQ actions into a per-MSI-Queue data structure,
and dispatch them form there, but the generic IRQ layer doesn't
provide a way to do that right now.
So, the current kludge is to "ACK" the interrupt by processing the
MSI Queue data structures and ACK'ing them, then we run the actual
handler like normal.
We are wasting a lot of useful information, for example the MSI data
and address are provided with ever MSI, as well as a system tick if
available. If we could pass this into the IRQ handler it could help
with certain things, in particular for PCI-Express error messages.
The MSI entries on sparc64 also tell you exactly which bus/device/fn
sent the MSI, which would be great for error handling when no
registered IRQ handler can service the interrupt.
We override the disable/enable IRQ chip methods in sun4v_msi, so we
have to call {mask,unmask}_msi_irq() directly from there. This is
another ugly wart.
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-11 08:41:02 +07:00
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2016-10-29 00:12:41 +07:00
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/* Sun4v HV IOMMU v2 APIs */
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unsigned long pci_sun4v_iotsb_conf(unsigned long devhandle,
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unsigned long ra,
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unsigned long table_size,
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unsigned long page_size,
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unsigned long dvma_base,
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u64 *iotsb_num);
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2016-10-29 00:12:43 +07:00
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unsigned long pci_sun4v_iotsb_bind(unsigned long devhandle,
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unsigned long iotsb_num,
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unsigned int pci_device);
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2016-10-29 00:12:44 +07:00
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unsigned long pci_sun4v_iotsb_map(unsigned long devhandle,
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unsigned long iotsb_num,
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unsigned long iotsb_index_iottes,
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unsigned long io_attributes,
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unsigned long io_page_list_pa,
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long *mapped);
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unsigned long pci_sun4v_iotsb_demap(unsigned long devhandle,
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unsigned long iotsb_num,
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unsigned long iotsb_index,
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unsigned long iottes,
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unsigned long *demapped);
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2006-02-10 13:05:54 +07:00
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#endif /* !(_PCI_SUN4V_H) */
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