2010-01-26 08:11:04 +07:00
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/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
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2008-10-21 20:07:09 +07:00
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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2008-10-31 23:14:59 +07:00
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#include <linux/i2c.h>
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2008-11-19 22:41:34 +07:00
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#include <linux/fb.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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2009-01-27 23:18:01 +07:00
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#include <linux/smsc911x.h>
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2009-11-03 21:42:06 +07:00
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#include <linux/regulator/fixed.h>
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2008-11-19 22:41:34 +07:00
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2009-02-17 22:59:38 +07:00
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#ifdef CONFIG_SMDK6410_WM1190_EV1
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#include <linux/mfd/wm8350/core.h>
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#include <linux/mfd/wm8350/pmic.h>
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#endif
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2008-11-19 22:41:34 +07:00
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#include <video/platform_lcd.h>
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2008-10-21 20:07:09 +07:00
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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2008-11-19 22:41:34 +07:00
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#include <mach/regs-fb.h>
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2008-10-21 20:07:09 +07:00
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#include <mach/map.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <plat/regs-serial.h>
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2010-01-26 08:45:40 +07:00
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#include <mach/regs-modem.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-sys.h>
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#include <mach/regs-srom.h>
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2008-10-31 23:14:52 +07:00
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#include <plat/iic.h>
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2008-11-19 22:41:34 +07:00
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#include <plat/fb.h>
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2009-01-27 23:18:01 +07:00
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#include <plat/gpio-cfg.h>
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2008-10-21 20:07:09 +07:00
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#include <plat/s3c6410.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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2009-06-29 18:03:41 +07:00
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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2008-10-21 20:07:09 +07:00
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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2009-06-29 18:03:41 +07:00
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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},
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[3] = {
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.hwport = 3,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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2008-10-21 20:07:09 +07:00
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},
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};
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2008-11-19 22:41:34 +07:00
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/* framebuffer and LCD setup. */
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/* GPF15 = LCD backlight control
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* GPF13 => Panel power
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* GPN5 = LCD nRESET signal
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* PWM_TOUT1 => backlight brightness
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*/
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static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
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unsigned int power)
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{
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if (power) {
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gpio_direction_output(S3C64XX_GPF(13), 1);
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gpio_direction_output(S3C64XX_GPF(15), 1);
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/* fire nRESET on power up */
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gpio_direction_output(S3C64XX_GPN(5), 0);
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msleep(10);
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gpio_direction_output(S3C64XX_GPN(5), 1);
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msleep(1);
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} else {
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gpio_direction_output(S3C64XX_GPF(15), 0);
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gpio_direction_output(S3C64XX_GPF(13), 0);
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}
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}
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static struct plat_lcd_data smdk6410_lcd_power_data = {
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.set_power = smdk6410_lcd_power_set,
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};
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static struct platform_device smdk6410_lcd_powerdev = {
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.name = "platform-lcd",
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.dev.parent = &s3c_device_fb.dev,
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.dev.platform_data = &smdk6410_lcd_power_data,
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};
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static struct s3c_fb_pd_win smdk6410_fb_win0 = {
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/* this is to ensure we use win0 */
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.win_mode = {
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.pixclock = 41094,
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.left_margin = 8,
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.right_margin = 13,
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.upper_margin = 7,
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.lower_margin = 5,
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.hsync_len = 3,
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.vsync_len = 1,
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.xres = 800,
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.yres = 480,
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},
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.max_bpp = 32,
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.default_bpp = 16,
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};
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/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
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static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
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.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
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.win[0] = &smdk6410_fb_win0,
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.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
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};
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2009-12-29 21:40:43 +07:00
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/*
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* Configuring Ethernet on SMDK6410
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*
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* Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
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* The constant address below corresponds to nCS1
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*
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* 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
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* 2) CFG6 needs to be switched to "LAN9115" side
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*/
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2009-01-27 23:18:01 +07:00
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static struct resource smdk6410_smsc911x_resources[] = {
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[0] = {
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2009-12-29 21:40:36 +07:00
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.start = S3C64XX_PA_XM0CSN1,
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.end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
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2009-01-27 23:18:01 +07:00
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = S3C_EINT(10),
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.end = S3C_EINT(10),
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.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
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},
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};
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static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
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.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
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.phy_interface = PHY_INTERFACE_MODE_MII,
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};
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static struct platform_device smdk6410_smsc911x = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
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.resource = &smdk6410_smsc911x_resources[0],
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.dev = {
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.platform_data = &smdk6410_smsc911x_pdata,
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},
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};
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2009-11-03 21:42:06 +07:00
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#ifdef CONFIG_REGULATOR
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static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
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{
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/* WM8580 */
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.supply = "PVDD",
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.dev_name = "0-001b",
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},
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{
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/* WM8580 */
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.supply = "AVDD",
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.dev_name = "0-001b",
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},
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};
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static struct regulator_init_data smdk6410_b_pwr_5v_data = {
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.constraints = {
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.always_on = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
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.consumer_supplies = smdk6410_b_pwr_5v_consumers,
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};
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static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
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.supply_name = "B_PWR_5V",
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.microvolts = 5000000,
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.init_data = &smdk6410_b_pwr_5v_data,
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2010-01-13 20:57:04 +07:00
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.gpio = -EINVAL,
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2009-11-03 21:42:06 +07:00
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};
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static struct platform_device smdk6410_b_pwr_5v = {
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.name = "reg-fixed-voltage",
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.id = -1,
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.dev = {
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.platform_data = &smdk6410_b_pwr_5v_pdata,
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},
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};
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#endif
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2009-01-23 23:29:43 +07:00
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static struct map_desc smdk6410_iodesc[] = {};
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2008-10-21 20:07:09 +07:00
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static struct platform_device *smdk6410_devices[] __initdata = {
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2008-11-04 03:14:53 +07:00
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#ifdef CONFIG_SMDK6410_SD_CH0
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2008-10-31 23:14:29 +07:00
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&s3c_device_hsmmc0,
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2008-11-04 03:14:53 +07:00
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#endif
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#ifdef CONFIG_SMDK6410_SD_CH1
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&s3c_device_hsmmc1,
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#endif
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2008-10-31 23:14:52 +07:00
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&s3c_device_i2c0,
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2008-10-31 23:14:57 +07:00
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&s3c_device_i2c1,
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2008-11-19 22:41:34 +07:00
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&s3c_device_fb,
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2009-11-23 07:13:39 +07:00
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&s3c_device_ohci,
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2009-05-17 04:11:20 +07:00
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&s3c_device_usb_hsotg,
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2009-11-03 21:42:06 +07:00
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#ifdef CONFIG_REGULATOR
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&smdk6410_b_pwr_5v,
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#endif
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2008-11-19 22:41:34 +07:00
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&smdk6410_lcd_powerdev,
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2009-01-27 23:18:01 +07:00
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&smdk6410_smsc911x,
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2008-10-21 20:07:09 +07:00
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};
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2009-02-17 22:59:38 +07:00
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#ifdef CONFIG_SMDK6410_WM1190_EV1
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/* S3C64xx internal logic & PLL */
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static struct regulator_init_data wm8350_dcdc1_data = {
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.constraints = {
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.name = "PVDD_INT/PVDD_PLL",
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.min_uV = 1200000,
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.max_uV = 1200000,
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.always_on = 1,
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.apply_uV = 1,
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},
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};
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/* Memory */
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static struct regulator_init_data wm8350_dcdc3_data = {
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.constraints = {
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.name = "PVDD_MEM",
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.min_uV = 1800000,
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.max_uV = 1800000,
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.always_on = 1,
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.state_mem = {
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.uV = 1800000,
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.mode = REGULATOR_MODE_NORMAL,
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.enabled = 1,
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},
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.initial_state = PM_SUSPEND_MEM,
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},
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};
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/* USB, EXT, PCM, ADC/DAC, USB, MMC */
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2009-11-03 21:42:06 +07:00
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static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
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{
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/* WM8580 */
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.supply = "DVDD",
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.dev_name = "0-001b",
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},
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};
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2009-02-17 22:59:38 +07:00
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static struct regulator_init_data wm8350_dcdc4_data = {
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.constraints = {
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.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
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.min_uV = 3000000,
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.max_uV = 3000000,
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.always_on = 1,
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},
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2009-11-03 21:42:06 +07:00
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.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
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.consumer_supplies = wm8350_dcdc4_consumers,
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2009-02-17 22:59:38 +07:00
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};
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/* ARM core */
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2009-04-15 23:11:53 +07:00
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static struct regulator_consumer_supply dcdc6_consumers[] = {
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{
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.supply = "vddarm",
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}
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};
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2009-02-17 22:59:38 +07:00
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static struct regulator_init_data wm8350_dcdc6_data = {
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.constraints = {
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.name = "PVDD_ARM",
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.min_uV = 1000000,
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.max_uV = 1300000,
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.always_on = 1,
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2009-04-15 23:11:53 +07:00
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
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2009-02-17 22:59:38 +07:00
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},
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2009-04-15 23:11:53 +07:00
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.num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
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.consumer_supplies = dcdc6_consumers,
|
2008-10-21 20:07:09 +07:00
|
|
|
};
|
|
|
|
|
2009-02-17 22:59:38 +07:00
|
|
|
/* Alive */
|
|
|
|
static struct regulator_init_data wm8350_ldo1_data = {
|
|
|
|
.constraints = {
|
|
|
|
.name = "PVDD_ALIVE",
|
|
|
|
.min_uV = 1200000,
|
|
|
|
.max_uV = 1200000,
|
|
|
|
.always_on = 1,
|
|
|
|
.apply_uV = 1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* OTG */
|
|
|
|
static struct regulator_init_data wm8350_ldo2_data = {
|
|
|
|
.constraints = {
|
|
|
|
.name = "PVDD_OTG",
|
|
|
|
.min_uV = 3300000,
|
|
|
|
.max_uV = 3300000,
|
2009-04-09 22:30:40 +07:00
|
|
|
.always_on = 1,
|
2009-02-17 22:59:38 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* LCD */
|
|
|
|
static struct regulator_init_data wm8350_ldo3_data = {
|
|
|
|
.constraints = {
|
|
|
|
.name = "PVDD_LCD",
|
|
|
|
.min_uV = 3000000,
|
|
|
|
.max_uV = 3000000,
|
2009-04-09 22:30:40 +07:00
|
|
|
.always_on = 1,
|
2009-02-17 22:59:38 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/* OTGi/1190-EV1 HPVDD & AVDD */
|
|
|
|
static struct regulator_init_data wm8350_ldo4_data = {
|
|
|
|
.constraints = {
|
|
|
|
.name = "PVDD_OTGI/HPVDD/AVDD",
|
|
|
|
.min_uV = 1200000,
|
|
|
|
.max_uV = 1200000,
|
|
|
|
.apply_uV = 1,
|
2009-04-09 22:30:40 +07:00
|
|
|
.always_on = 1,
|
2009-02-17 22:59:38 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct {
|
|
|
|
int regulator;
|
|
|
|
struct regulator_init_data *initdata;
|
|
|
|
} wm1190_regulators[] = {
|
|
|
|
{ WM8350_DCDC_1, &wm8350_dcdc1_data },
|
|
|
|
{ WM8350_DCDC_3, &wm8350_dcdc3_data },
|
|
|
|
{ WM8350_DCDC_4, &wm8350_dcdc4_data },
|
|
|
|
{ WM8350_DCDC_6, &wm8350_dcdc6_data },
|
|
|
|
{ WM8350_LDO_1, &wm8350_ldo1_data },
|
|
|
|
{ WM8350_LDO_2, &wm8350_ldo2_data },
|
|
|
|
{ WM8350_LDO_3, &wm8350_ldo3_data },
|
|
|
|
{ WM8350_LDO_4, &wm8350_ldo4_data },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-11-03 21:42:04 +07:00
|
|
|
/* Configure the IRQ line */
|
|
|
|
s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
|
|
|
|
|
2009-02-17 22:59:38 +07:00
|
|
|
/* Instantiate the regulators */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
|
|
|
|
wm8350_register_regulator(wm8350,
|
|
|
|
wm1190_regulators[i].regulator,
|
|
|
|
wm1190_regulators[i].initdata);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
|
|
|
|
.init = smdk6410_wm8350_init,
|
2009-04-10 01:00:19 +07:00
|
|
|
.irq_high = 1,
|
2010-01-19 22:26:56 +07:00
|
|
|
.irq_base = IRQ_BOARD_START,
|
2009-02-17 22:59:38 +07:00
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2008-10-31 23:14:59 +07:00
|
|
|
static struct i2c_board_info i2c_devs0[] __initdata = {
|
|
|
|
{ I2C_BOARD_INFO("24c08", 0x50), },
|
2009-01-23 23:29:41 +07:00
|
|
|
{ I2C_BOARD_INFO("wm8580", 0x1b), },
|
2009-02-17 22:59:38 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
|
|
|
{ I2C_BOARD_INFO("wm8350", 0x1a),
|
|
|
|
.platform_data = &smdk6410_wm8350_pdata,
|
|
|
|
.irq = S3C_EINT(12),
|
|
|
|
},
|
|
|
|
#endif
|
2008-10-31 23:14:59 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct i2c_board_info i2c_devs1[] __initdata = {
|
|
|
|
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
|
2008-10-21 20:07:09 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static void __init smdk6410_map_io(void)
|
|
|
|
{
|
2008-12-12 07:24:40 +07:00
|
|
|
u32 tmp;
|
|
|
|
|
2008-10-21 20:07:09 +07:00
|
|
|
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
|
|
|
|
s3c24xx_init_clocks(12000000);
|
|
|
|
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
|
2008-12-12 07:24:40 +07:00
|
|
|
|
|
|
|
/* set the LCD type */
|
|
|
|
|
|
|
|
tmp = __raw_readl(S3C64XX_SPCON);
|
|
|
|
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
|
|
|
|
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
|
|
|
|
__raw_writel(tmp, S3C64XX_SPCON);
|
|
|
|
|
|
|
|
/* remove the lcd bypass */
|
|
|
|
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
|
|
|
|
tmp &= ~MIFPCON_LCD_BYPASS;
|
|
|
|
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
|
2008-10-21 20:07:09 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init smdk6410_machine_init(void)
|
|
|
|
{
|
2009-12-29 21:40:36 +07:00
|
|
|
u32 cs1;
|
|
|
|
|
2008-10-31 23:14:52 +07:00
|
|
|
s3c_i2c0_set_platdata(NULL);
|
2008-10-31 23:14:57 +07:00
|
|
|
s3c_i2c1_set_platdata(NULL);
|
2008-11-19 22:41:34 +07:00
|
|
|
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
|
2008-10-31 23:14:59 +07:00
|
|
|
|
2009-12-29 21:40:36 +07:00
|
|
|
/* configure nCS1 width to 16 bits */
|
|
|
|
|
|
|
|
cs1 = __raw_readl(S3C64XX_SROM_BW) &
|
|
|
|
~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
|
|
|
|
cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
|
|
|
|
(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
|
|
|
|
(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
|
|
|
|
S3C64XX_SROM_BW__NCS1__SHIFT;
|
|
|
|
__raw_writel(cs1, S3C64XX_SROM_BW);
|
|
|
|
|
|
|
|
/* set timing for nCS1 suitable for ethernet chip */
|
|
|
|
|
|
|
|
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
|
|
|
|
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
|
|
|
|
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
|
|
|
|
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
|
|
|
|
(0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
|
|
|
|
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
|
|
|
|
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
|
|
|
|
|
2009-04-08 22:12:35 +07:00
|
|
|
gpio_request(S3C64XX_GPN(5), "LCD power");
|
|
|
|
gpio_request(S3C64XX_GPF(13), "LCD power");
|
|
|
|
gpio_request(S3C64XX_GPF(15), "LCD power");
|
|
|
|
|
2008-10-31 23:14:59 +07:00
|
|
|
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
|
|
|
|
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
|
|
|
|
|
2008-10-21 20:07:09 +07:00
|
|
|
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
|
|
|
|
}
|
|
|
|
|
|
|
|
MACHINE_START(SMDK6410, "SMDK6410")
|
|
|
|
/* Maintainer: Ben Dooks <ben@fluff.org> */
|
|
|
|
.phys_io = S3C_PA_UART & 0xfff00000,
|
|
|
|
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
|
|
|
|
.boot_params = S3C64XX_PA_SDRAM + 0x100,
|
|
|
|
|
|
|
|
.init_irq = s3c6410_init_irq,
|
|
|
|
.map_io = smdk6410_map_io,
|
|
|
|
.init_machine = smdk6410_machine_init,
|
|
|
|
.timer = &s3c24xx_timer,
|
|
|
|
MACHINE_END
|