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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
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#ifndef _PPC64_CACHEFLUSH_H
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#define _PPC64_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/cputable.h>
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/*
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* No cache flushing is required when address mappings are
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* changed, because the caches on PowerPCs are physically
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* addressed.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void __flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
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extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy(dst, src, len); \
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flush_icache_user_range(vma, page, vaddr, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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extern void __flush_dcache_icache(void *page_va);
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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__flush_icache_range(start, stop);
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}
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#endif /* _PPC64_CACHEFLUSH_H */
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