License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-10-23 12:26:29 +07:00
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#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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2007-10-17 23:04:40 +07:00
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2012-12-15 05:37:13 +07:00
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#include <uapi/asm/mce.h>
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2007-10-17 23:04:40 +07:00
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2012-12-21 23:03:58 +07:00
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/*
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* Machine Check support for x86
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*/
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/* MCG_CAP register defines */
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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2018-09-25 07:01:27 +07:00
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#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
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#define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
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#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
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2012-12-21 23:03:58 +07:00
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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2018-09-25 07:01:27 +07:00
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#define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
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#define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
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#define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
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2012-12-21 23:03:58 +07:00
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/* MCG_STATUS register defines */
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2018-09-25 07:01:27 +07:00
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#define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
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#define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
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#define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
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2015-06-04 23:55:22 +07:00
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/* MCG_EXT_CTL register defines */
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2018-09-25 07:01:27 +07:00
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#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
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2012-12-21 23:03:58 +07:00
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/* MCi_STATUS register defines */
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2018-09-25 07:01:27 +07:00
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#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
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#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
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#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
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#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
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#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
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#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
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#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
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#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
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2018-09-25 07:03:43 +07:00
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#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
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#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
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#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
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2013-07-25 03:54:20 +07:00
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2014-11-18 09:09:19 +07:00
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/* AMD-specific bits */
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2018-09-25 07:01:27 +07:00
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#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
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#define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
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#define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
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#define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
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2019-02-13 04:24:28 +07:00
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#define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */
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2016-03-07 20:02:18 +07:00
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/*
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* McaX field if set indicates a given bank supports MCA extensions:
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* - Deferred error interrupt type is specifiable by bank.
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* - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
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* But should not be used to determine MSR numbers.
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* - TCC bit is present in MCx_STATUS.
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*/
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#define MCI_CONFIG_MCAX 0x1
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#define MCI_IPID_MCATYPE 0xFFFF0000
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#define MCI_IPID_HWID 0xFFF
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2014-11-18 09:09:19 +07:00
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2013-07-25 03:54:20 +07:00
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/*
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* Note that the full MCACOD field of IA32_MCi_STATUS MSR is
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* bits 15:0. But bit 12 is the 'F' bit, defined for corrected
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* errors to indicate that errors are being filtered by hardware.
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* We should mask out bit 12 when looking for specific signatures
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* of uncorrected errors - so the F bit is deliberately skipped
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* in this #define.
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*/
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#define MCACOD 0xefff /* MCA Error Code */
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2012-12-21 23:03:58 +07:00
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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2013-07-25 03:54:20 +07:00
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#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
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2012-12-21 23:03:58 +07:00
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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2018-09-25 07:01:27 +07:00
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#define MCI_CTL2_CMCI_EN BIT_ULL(30)
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2012-12-21 23:03:58 +07:00
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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2013-06-05 01:54:14 +07:00
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#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
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2012-12-21 23:03:58 +07:00
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_LEN 32
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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2016-03-07 20:02:17 +07:00
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/* AMD Scalable MCA */
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2016-04-30 19:33:54 +07:00
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#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
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#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
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#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
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2016-03-07 20:02:19 +07:00
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#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
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2016-03-07 20:02:17 +07:00
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#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
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2016-03-07 20:02:18 +07:00
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#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
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2016-09-12 14:59:28 +07:00
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#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
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2016-05-11 19:58:23 +07:00
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#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
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#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
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2016-03-07 20:02:19 +07:00
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#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
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2016-04-30 19:33:54 +07:00
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#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
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#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
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#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
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2016-03-07 20:02:19 +07:00
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#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
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2016-03-07 20:02:17 +07:00
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#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
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2016-03-07 20:02:18 +07:00
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#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
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2016-09-12 14:59:28 +07:00
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#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
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2016-05-11 19:58:23 +07:00
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#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
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#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
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2016-03-07 20:02:19 +07:00
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#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
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2016-03-07 20:02:17 +07:00
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2012-12-21 23:03:58 +07:00
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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2017-03-27 16:33:01 +07:00
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struct mce_log_buffer {
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2012-12-21 23:03:58 +07:00
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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2012-10-15 23:03:57 +07:00
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2017-01-24 01:35:14 +07:00
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enum mce_notifier_prios {
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2017-03-27 16:33:02 +07:00
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MCE_PRIO_FIRST = INT_MAX,
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MCE_PRIO_SRAO = INT_MAX - 1,
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MCE_PRIO_EXTLOG = INT_MAX - 2,
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MCE_PRIO_NFIT = INT_MAX - 3,
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MCE_PRIO_EDAC = INT_MAX - 4,
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2017-03-27 16:33:03 +07:00
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MCE_PRIO_MCELOG = 1,
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2017-01-24 01:35:14 +07:00
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MCE_PRIO_LOWEST = 0,
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};
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2018-08-17 17:01:36 +07:00
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struct notifier_block;
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2015-08-12 23:29:38 +07:00
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extern void mce_register_decode_chain(struct notifier_block *nb);
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2011-12-04 21:12:09 +07:00
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extern void mce_unregister_decode_chain(struct notifier_block *nb);
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2010-01-04 23:17:21 +07:00
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2009-06-15 15:22:15 +07:00
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#include <linux/percpu.h>
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2011-07-27 06:09:06 +07:00
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#include <linux/atomic.h>
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2009-06-15 15:22:15 +07:00
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2009-06-15 15:22:49 +07:00
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extern int mce_p5_enabled;
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2007-10-17 23:04:40 +07:00
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2009-06-15 15:27:47 +07:00
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#ifdef CONFIG_X86_MCE
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2009-11-10 08:38:24 +07:00
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int mcheck_init(void);
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2009-10-16 17:31:32 +07:00
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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2015-08-12 23:29:40 +07:00
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void mcheck_cpu_clear(struct cpuinfo_x86 *c);
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2015-03-23 22:42:53 +07:00
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void mcheck_vendor_init_severity(void);
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2009-06-15 15:27:47 +07:00
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#else
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2009-11-10 08:38:24 +07:00
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static inline int mcheck_init(void) { return 0; }
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2009-10-16 17:31:32 +07:00
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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2015-08-12 23:29:40 +07:00
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static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
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2015-03-23 22:42:53 +07:00
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static inline void mcheck_vendor_init_severity(void) {}
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2009-06-15 15:27:47 +07:00
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#endif
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|
|
|
|
2009-06-15 15:22:15 +07:00
|
|
|
#ifdef CONFIG_X86_ANCIENT_MCE
|
|
|
|
|
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
|
|
|
|
|
void winchip_mcheck_init(struct cpuinfo_x86 *c);
|
2009-06-15 15:22:49 +07:00
|
|
|
static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
|
2009-06-15 15:22:15 +07:00
|
|
|
#else
|
|
|
|
|
static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
|
|
|
|
|
static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
|
2009-06-15 15:22:49 +07:00
|
|
|
static inline void enable_p5_mce(void) {}
|
2009-06-15 15:22:15 +07:00
|
|
|
#endif
|
|
|
|
|
|
2009-02-12 19:43:22 +07:00
|
|
|
void mce_setup(struct mce *m);
|
2007-10-17 23:04:40 +07:00
|
|
|
void mce_log(struct mce *m);
|
2012-01-27 06:49:14 +07:00
|
|
|
DECLARE_PER_CPU(struct device *, mce_device);
|
2007-10-17 23:04:40 +07:00
|
|
|
|
2009-02-12 19:49:30 +07:00
|
|
|
/*
|
2009-07-09 05:31:45 +07:00
|
|
|
* Maximum banks number.
|
|
|
|
|
* This is the limit of the current register layout on
|
|
|
|
|
* Intel CPUs.
|
2009-02-12 19:49:30 +07:00
|
|
|
*/
|
2009-07-09 05:31:45 +07:00
|
|
|
#define MAX_NR_BANKS 32
|
2009-02-12 19:49:30 +07:00
|
|
|
|
2007-10-17 23:04:40 +07:00
|
|
|
#ifdef CONFIG_X86_MCE_INTEL
|
|
|
|
|
void mce_intel_feature_init(struct cpuinfo_x86 *c);
|
2015-08-12 23:29:40 +07:00
|
|
|
void mce_intel_feature_clear(struct cpuinfo_x86 *c);
|
2009-02-12 19:49:36 +07:00
|
|
|
void cmci_clear(void);
|
|
|
|
|
void cmci_reenable(void);
|
2013-03-20 17:01:29 +07:00
|
|
|
void cmci_rediscover(void);
|
2009-02-12 19:49:36 +07:00
|
|
|
void cmci_recheck(void);
|
2007-10-17 23:04:40 +07:00
|
|
|
#else
|
|
|
|
|
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
|
2015-08-12 23:29:40 +07:00
|
|
|
static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
|
2009-02-12 19:49:36 +07:00
|
|
|
static inline void cmci_clear(void) {}
|
|
|
|
|
static inline void cmci_reenable(void) {}
|
2013-03-20 17:01:29 +07:00
|
|
|
static inline void cmci_rediscover(void) {}
|
2009-02-12 19:49:36 +07:00
|
|
|
static inline void cmci_recheck(void) {}
|
2007-10-17 23:04:40 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86_MCE_AMD
|
|
|
|
|
void mce_amd_feature_init(struct cpuinfo_x86 *c);
|
2016-11-18 05:57:27 +07:00
|
|
|
int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
|
2007-10-17 23:04:40 +07:00
|
|
|
#else
|
|
|
|
|
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
|
2016-11-18 05:57:27 +07:00
|
|
|
static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
|
2007-10-17 23:04:40 +07:00
|
|
|
#endif
|
|
|
|
|
|
2018-09-23 16:36:04 +07:00
|
|
|
static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
|
|
|
|
|
|
2009-05-29 00:05:33 +07:00
|
|
|
int mce_available(struct cpuinfo_x86 *c);
|
2017-05-19 16:39:09 +07:00
|
|
|
bool mce_is_memory_error(struct mce *m);
|
2018-10-26 07:37:28 +07:00
|
|
|
bool mce_is_correctable(struct mce *m);
|
2018-10-26 07:37:29 +07:00
|
|
|
int mce_usable_address(struct mce *m);
|
2009-02-12 19:49:36 +07:00
|
|
|
|
2009-05-28 02:56:52 +07:00
|
|
|
DECLARE_PER_CPU(unsigned, mce_exception_count);
|
2009-05-28 02:56:57 +07:00
|
|
|
DECLARE_PER_CPU(unsigned, mce_poll_count);
|
2009-05-28 02:56:52 +07:00
|
|
|
|
2009-02-12 19:49:34 +07:00
|
|
|
typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
|
|
|
|
|
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
|
|
|
|
|
|
2009-02-12 19:43:23 +07:00
|
|
|
enum mcp_flags {
|
x86/MCE/intel: Cleanup CMCI storm logic
Initially, this started with the yet another report about a race
condition in the CMCI storm adaptive period length thing. Yes, we have
to admit, it is fragile and error prone. So let's simplify it.
The simpler logic is: now, after we enter storm mode, we go straight to
polling with CMCI_STORM_INTERVAL, i.e. once a second. We remain in storm
mode as long as we see errors being logged while polling.
Theoretically, if we see an uninterrupted error stream, we will remain
in storm mode indefinitely and keep polling the MSRs.
However, when the storm is actually a burst of errors, once we have
logged them all, we back out of it after ~5 mins of polling and no more
errors logged.
If we encounter an error during those 5 minutes, we reset the polling
interval to 5 mins.
Making machine_check_poll() return a bool and denoting whether it has
seen an error or not lets us simplify a bunch of code and move the storm
handling private to mce_intel.c.
Some minor cleanups while at it.
Reported-by: Calvin Owens <calvinowens@fb.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1417746575-23299-1-git-send-email-calvinowens@fb.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-13 21:08:51 +07:00
|
|
|
MCP_TIMESTAMP = BIT(0), /* log time stamp */
|
|
|
|
|
MCP_UC = BIT(1), /* log uncorrected errors */
|
|
|
|
|
MCP_DONTLOG = BIT(2), /* only clear, don't log */
|
2009-02-12 19:43:23 +07:00
|
|
|
};
|
x86/MCE/intel: Cleanup CMCI storm logic
Initially, this started with the yet another report about a race
condition in the CMCI storm adaptive period length thing. Yes, we have
to admit, it is fragile and error prone. So let's simplify it.
The simpler logic is: now, after we enter storm mode, we go straight to
polling with CMCI_STORM_INTERVAL, i.e. once a second. We remain in storm
mode as long as we see errors being logged while polling.
Theoretically, if we see an uninterrupted error stream, we will remain
in storm mode indefinitely and keep polling the MSRs.
However, when the storm is actually a burst of errors, once we have
logged them all, we back out of it after ~5 mins of polling and no more
errors logged.
If we encounter an error during those 5 minutes, we reset the polling
interval to 5 mins.
Making machine_check_poll() return a bool and denoting whether it has
seen an error or not lets us simplify a bunch of code and move the storm
handling private to mce_intel.c.
Some minor cleanups while at it.
Reported-by: Calvin Owens <calvinowens@fb.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1417746575-23299-1-git-send-email-calvinowens@fb.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-13 21:08:51 +07:00
|
|
|
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
|
2009-02-12 19:43:23 +07:00
|
|
|
|
2009-05-28 02:56:58 +07:00
|
|
|
int mce_notify_irq(void);
|
2007-10-17 23:04:40 +07:00
|
|
|
|
2009-04-30 00:31:00 +07:00
|
|
|
DECLARE_PER_CPU(struct mce, injectm);
|
2011-11-04 01:46:47 +07:00
|
|
|
|
2013-07-01 22:38:47 +07:00
|
|
|
/* Disable CMCI/polling for MCA bank claimed by firmware */
|
|
|
|
|
extern void mce_disable_bank(int bank);
|
|
|
|
|
|
2009-06-15 15:27:47 +07:00
|
|
|
/*
|
|
|
|
|
* Exception handler
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Call the installed machine check handler for this CPU setup. */
|
|
|
|
|
extern void (*machine_check_vector)(struct pt_regs *, long error_code);
|
|
|
|
|
void do_machine_check(struct pt_regs *, long);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Threshold handler
|
|
|
|
|
*/
|
2009-02-12 19:49:31 +07:00
|
|
|
extern void (*mce_threshold_vector)(void);
|
|
|
|
|
|
2015-05-06 18:58:56 +07:00
|
|
|
/* Deferred error interrupt handler */
|
|
|
|
|
extern void (*deferred_error_int_vector)(void);
|
|
|
|
|
|
2009-06-15 15:24:40 +07:00
|
|
|
/*
|
|
|
|
|
* Thermal handler
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
void intel_init_thermal(struct cpuinfo_x86 *c);
|
|
|
|
|
|
2011-01-03 18:52:04 +07:00
|
|
|
/* Interrupt Handler for core thermal thresholds */
|
|
|
|
|
extern int (*platform_thermal_notify)(__u64 msr_val);
|
|
|
|
|
|
2013-05-18 06:42:01 +07:00
|
|
|
/* Interrupt Handler for package thermal thresholds */
|
|
|
|
|
extern int (*platform_thermal_package_notify)(__u64 msr_val);
|
|
|
|
|
|
|
|
|
|
/* Callback support of rate control, return true, if
|
|
|
|
|
* callback has rate control */
|
|
|
|
|
extern bool (*platform_thermal_package_rate_control)(void);
|
|
|
|
|
|
2009-11-10 08:38:24 +07:00
|
|
|
#ifdef CONFIG_X86_THERMAL_VECTOR
|
|
|
|
|
extern void mcheck_intel_therm_init(void);
|
|
|
|
|
#else
|
|
|
|
|
static inline void mcheck_intel_therm_init(void) { }
|
|
|
|
|
#endif
|
|
|
|
|
|
ACPI, APEI, Generic Hardware Error Source memory error support
Generic Hardware Error Source provides a way to report platform
hardware errors (such as that from chipset). It works in so called
"Firmware First" mode, that is, hardware errors are reported to
firmware firstly, then reported to Linux by firmware. This way, some
non-standard hardware error registers or non-standard hardware link
can be checked by firmware to produce more valuable hardware error
information for Linux.
Now, only SCI notification type and memory errors are supported. More
notification type and hardware error type will be added later. These
memory errors are reported to user space through /dev/mcelog via
faking a corrected Machine Check, so that the error memory page can be
offlined by /sbin/mcelog if the error count for one page is beyond the
threshold.
On some machines, Machine Check can not report physical address for
some corrected memory errors, but GHES can do that. So this simplified
GHES is implemented firstly.
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2010-05-18 13:35:20 +07:00
|
|
|
/*
|
|
|
|
|
* Used by APEI to report memory error via /dev/mcelog
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct cper_sec_mem_err;
|
|
|
|
|
extern void apei_mce_report_mem_error(int corrected,
|
|
|
|
|
struct cper_sec_mem_err *mem_err);
|
|
|
|
|
|
2016-03-07 20:02:18 +07:00
|
|
|
/*
|
|
|
|
|
* Enumerate new IP types and HWID values in AMD processors which support
|
|
|
|
|
* Scalable MCA.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_X86_MCE_AMD
|
|
|
|
|
|
2016-09-12 14:59:34 +07:00
|
|
|
/* These may be used by multiple smca_hwid_mcatypes */
|
|
|
|
|
enum smca_bank_types {
|
2016-03-07 20:02:18 +07:00
|
|
|
SMCA_LS = 0, /* Load Store */
|
|
|
|
|
SMCA_IF, /* Instruction Fetch */
|
2016-09-12 14:59:34 +07:00
|
|
|
SMCA_L2_CACHE, /* L2 Cache */
|
|
|
|
|
SMCA_DE, /* Decoder Unit */
|
x86/mce/AMD, EDAC/mce_amd: Enumerate Reserved SMCA bank type
Currently, bank 4 is reserved on Fam17h, so we chose not to initialize
bank 4 in the smca_banks array. This means that when we check if a bank
is initialized, like during boot or resume, we will see that bank 4 is
not initialized and try to initialize it.
This will cause a call trace, when resuming from suspend, due to
rdmsr_*on_cpu() calls in the init path. The rdmsr_*on_cpu() calls issue
an IPI but we're running with interrupts disabled. This triggers:
WARNING: CPU: 0 PID: 11523 at kernel/smp.c:291 smp_call_function_single+0xdc/0xe0
...
Reserved banks will be read-as-zero, so their MCA_IPID register will be
zero. So, like the smca_banks array, the threshold_banks array will not
have an entry for a reserved bank since all its MCA_MISC* registers will
be zero.
Enumerate a "Reserved" bank type that matches on a HWID_MCATYPE of 0,0.
Use the "Reserved" type when checking if a bank is reserved. It's
possible that other bank numbers may be reserved on future systems.
Don't try to find the block address on reserved banks.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org> # 4.14.x
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20180221101900.10326-7-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2018-02-21 17:18:58 +07:00
|
|
|
SMCA_RESERVED, /* Reserved */
|
2016-09-12 14:59:34 +07:00
|
|
|
SMCA_EX, /* Execution Unit */
|
2016-03-07 20:02:18 +07:00
|
|
|
SMCA_FP, /* Floating Point */
|
2016-09-12 14:59:34 +07:00
|
|
|
SMCA_L3_CACHE, /* L3 Cache */
|
|
|
|
|
SMCA_CS, /* Coherent Slave */
|
x86/MCE/AMD, EDAC/mce_amd: Add new McaTypes for CS, PSP, and SMU units
The existing CS, PSP, and SMU SMCA bank types will see new versions (as
indicated by their McaTypes) in future SMCA systems.
Add the new (HWID, MCATYPE) tuples for these new versions. Reuse the
same names as the older versions, since they are logically the same to
the user. SMCA systems won't mix and match IP blocks with different
McaType versions in the same system, so there isn't a need to
distinguish them. The MCA_IPID register is saved when logging an MCA
error, and that can be used to triage the error.
Also, add the new error descriptions to edac_mce_amd. Some error types
(positions in the list) are overloaded compared to the previous
McaTypes. Therefore, just create new lists of the error descriptions to
keep things simple even if some of the error descriptions are the same
between versions.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Shirish S <Shirish.S@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190201225534.8177-3-Yazen.Ghannam@amd.com
2019-02-02 05:55:52 +07:00
|
|
|
SMCA_CS_V2, /* Coherent Slave */
|
2016-09-12 14:59:34 +07:00
|
|
|
SMCA_PIE, /* Power, Interrupts, etc. */
|
|
|
|
|
SMCA_UMC, /* Unified Memory Controller */
|
|
|
|
|
SMCA_PB, /* Parameter Block */
|
|
|
|
|
SMCA_PSP, /* Platform Security Processor */
|
x86/MCE/AMD, EDAC/mce_amd: Add new McaTypes for CS, PSP, and SMU units
The existing CS, PSP, and SMU SMCA bank types will see new versions (as
indicated by their McaTypes) in future SMCA systems.
Add the new (HWID, MCATYPE) tuples for these new versions. Reuse the
same names as the older versions, since they are logically the same to
the user. SMCA systems won't mix and match IP blocks with different
McaType versions in the same system, so there isn't a need to
distinguish them. The MCA_IPID register is saved when logging an MCA
error, and that can be used to triage the error.
Also, add the new error descriptions to edac_mce_amd. Some error types
(positions in the list) are overloaded compared to the previous
McaTypes. Therefore, just create new lists of the error descriptions to
keep things simple even if some of the error descriptions are the same
between versions.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Shirish S <Shirish.S@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190201225534.8177-3-Yazen.Ghannam@amd.com
2019-02-02 05:55:52 +07:00
|
|
|
SMCA_PSP_V2, /* Platform Security Processor */
|
2016-09-12 14:59:34 +07:00
|
|
|
SMCA_SMU, /* System Management Unit */
|
x86/MCE/AMD, EDAC/mce_amd: Add new McaTypes for CS, PSP, and SMU units
The existing CS, PSP, and SMU SMCA bank types will see new versions (as
indicated by their McaTypes) in future SMCA systems.
Add the new (HWID, MCATYPE) tuples for these new versions. Reuse the
same names as the older versions, since they are logically the same to
the user. SMCA systems won't mix and match IP blocks with different
McaType versions in the same system, so there isn't a need to
distinguish them. The MCA_IPID register is saved when logging an MCA
error, and that can be used to triage the error.
Also, add the new error descriptions to edac_mce_amd. Some error types
(positions in the list) are overloaded compared to the previous
McaTypes. Therefore, just create new lists of the error descriptions to
keep things simple even if some of the error descriptions are the same
between versions.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Shirish S <Shirish.S@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190201225534.8177-3-Yazen.Ghannam@amd.com
2019-02-02 05:55:52 +07:00
|
|
|
SMCA_SMU_V2, /* System Management Unit */
|
2019-02-02 05:55:51 +07:00
|
|
|
SMCA_MP5, /* Microprocessor 5 Unit */
|
|
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SMCA_NBIO, /* Northbridge IO Unit */
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SMCA_PCIE, /* PCI Express Unit */
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2016-09-12 14:59:34 +07:00
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N_SMCA_BANK_TYPES
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};
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x86/mce/AMD: Fix HWID_MCATYPE calculation by grouping arguments
The calculation of the hwid_mcatype value in get_smca_bank_info()
became incorrect after applying the following commit:
1ce9cd7f9f0b ("x86/RAS: Simplify SMCA HWID descriptor struct")
This causes the function to not match a bank to its type.
Disassembly of hwid_mcatype calculation after change:
db: 8b 45 e0 mov -0x20(%rbp),%eax
de: 41 89 c4 mov %eax,%r12d
e1: 25 00 00 ff 0f and $0xfff0000,%eax
e6: 41 c1 ec 10 shr $0x10,%r12d
ea: 41 09 c4 or %eax,%r12d
Disassembly of hwid_mcatype calculation in original code:
286: 8b 45 d0 mov -0x30(%rbp),%eax
289: 41 89 c5 mov %eax,%r13d
28c: c1 e8 10 shr $0x10,%eax
28f: 41 81 e5 ff 0f 00 00 and $0xfff,%r13d
296: 41 c1 e5 10 shl $0x10,%r13d
29a: 41 09 c5 or %eax,%r13d
Grouping the arguments to the HWID_MCATYPE() macro fixes the issue.
( Boris suggested adding parentheses in the macro. )
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-11-11 03:32:35 +07:00
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#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
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2016-03-07 20:02:18 +07:00
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2016-11-02 18:48:01 +07:00
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struct smca_hwid {
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2016-09-12 14:59:34 +07:00
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unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
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u32 hwid_mcatype; /* (hwid,mcatype) tuple */
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u32 xec_bitmap; /* Bitmap of valid ExtErrorCodes; current max is 21. */
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2017-01-24 01:35:08 +07:00
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u8 count; /* Number of instances. */
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2016-03-07 20:02:18 +07:00
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};
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2016-11-01 23:33:00 +07:00
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struct smca_bank {
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2016-11-02 18:48:01 +07:00
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struct smca_hwid *hwid;
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2017-01-24 01:35:08 +07:00
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u32 id; /* Value of MCA_IPID[InstanceId]. */
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u8 sysfs_id; /* Value used for sysfs name. */
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2016-09-12 14:59:34 +07:00
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};
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2016-11-01 23:33:00 +07:00
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extern struct smca_bank smca_banks[MAX_NR_BANKS];
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2016-09-12 14:59:34 +07:00
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2016-11-04 03:12:33 +07:00
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extern const char *smca_get_long_name(enum smca_bank_types t);
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2017-12-18 18:37:13 +07:00
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extern bool amd_mce_is_memory_error(struct mce *m);
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2016-12-13 10:25:04 +07:00
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2016-11-11 00:44:44 +07:00
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extern int mce_threshold_create_device(unsigned int cpu);
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extern int mce_threshold_remove_device(unsigned int cpu);
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2016-12-13 10:25:04 +07:00
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2016-11-11 00:44:44 +07:00
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#else
|
2016-09-12 14:59:34 +07:00
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2016-11-11 00:44:44 +07:00
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static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
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static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
|
2017-12-18 18:37:13 +07:00
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static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
|
2016-12-13 10:25:04 +07:00
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2016-03-07 20:02:18 +07:00
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#endif
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2008-10-23 12:26:29 +07:00
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#endif /* _ASM_X86_MCE_H */
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