2013-07-31 15:14:10 +07:00
|
|
|
/*
|
|
|
|
|
* Synopsys Designware PCIe host controller driver
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
|
|
|
|
* http://www.samsung.com
|
|
|
|
|
*
|
|
|
|
|
* Author: Jingoo Han <jg1.han@samsung.com>
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
|
*/
|
|
|
|
|
|
2013-10-09 22:12:21 +07:00
|
|
|
#ifndef _PCIE_DESIGNWARE_H
|
|
|
|
|
#define _PCIE_DESIGNWARE_H
|
|
|
|
|
|
2013-07-31 15:14:10 +07:00
|
|
|
struct pcie_port_info {
|
|
|
|
|
u32 cfg0_size;
|
|
|
|
|
u32 cfg1_size;
|
|
|
|
|
u32 io_size;
|
|
|
|
|
u32 mem_size;
|
|
|
|
|
phys_addr_t io_bus_addr;
|
|
|
|
|
phys_addr_t mem_bus_addr;
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-06 13:54:59 +07:00
|
|
|
/*
|
|
|
|
|
* Maximum number of MSI IRQs can be 256 per controller. But keep
|
|
|
|
|
* it 32 as of now. Probably we will never need more than 32. If needed,
|
|
|
|
|
* then increment it in multiple of 32.
|
|
|
|
|
*/
|
|
|
|
|
#define MAX_MSI_IRQS 32
|
|
|
|
|
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
|
|
|
|
|
|
2013-07-31 15:14:10 +07:00
|
|
|
struct pcie_port {
|
|
|
|
|
struct device *dev;
|
|
|
|
|
u8 root_bus_nr;
|
|
|
|
|
void __iomem *dbi_base;
|
|
|
|
|
u64 cfg0_base;
|
PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-17 16:00:41 +07:00
|
|
|
u64 cfg0_mod_base;
|
2013-07-31 15:14:10 +07:00
|
|
|
void __iomem *va_cfg0_base;
|
|
|
|
|
u64 cfg1_base;
|
PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-17 16:00:41 +07:00
|
|
|
u64 cfg1_mod_base;
|
2013-07-31 15:14:10 +07:00
|
|
|
void __iomem *va_cfg1_base;
|
|
|
|
|
u64 io_base;
|
PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-17 16:00:41 +07:00
|
|
|
u64 io_mod_base;
|
2013-07-31 15:14:10 +07:00
|
|
|
u64 mem_base;
|
PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-17 16:00:41 +07:00
|
|
|
u64 mem_mod_base;
|
2013-07-31 15:14:10 +07:00
|
|
|
struct resource cfg;
|
|
|
|
|
struct resource io;
|
|
|
|
|
struct resource mem;
|
2014-07-24 00:52:38 +07:00
|
|
|
struct resource busn;
|
2013-07-31 15:14:10 +07:00
|
|
|
struct pcie_port_info config;
|
|
|
|
|
int irq;
|
|
|
|
|
u32 lanes;
|
|
|
|
|
struct pcie_host_ops *ops;
|
2013-09-06 13:54:59 +07:00
|
|
|
int msi_irq;
|
2013-10-09 19:32:12 +07:00
|
|
|
struct irq_domain *irq_domain;
|
2013-09-06 13:54:59 +07:00
|
|
|
unsigned long msi_data;
|
|
|
|
|
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
|
2013-07-31 15:14:10 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct pcie_host_ops {
|
|
|
|
|
void (*readl_rc)(struct pcie_port *pp,
|
|
|
|
|
void __iomem *dbi_base, u32 *val);
|
|
|
|
|
void (*writel_rc)(struct pcie_port *pp,
|
|
|
|
|
u32 val, void __iomem *dbi_base);
|
|
|
|
|
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
|
|
|
|
|
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
|
2014-07-21 23:58:41 +07:00
|
|
|
int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
|
|
|
|
|
unsigned int devfn, int where, int size, u32 *val);
|
|
|
|
|
int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
|
|
|
|
|
unsigned int devfn, int where, int size, u32 val);
|
2013-07-31 15:14:10 +07:00
|
|
|
int (*link_up)(struct pcie_port *pp);
|
|
|
|
|
void (*host_init)(struct pcie_port *pp);
|
2014-07-21 23:58:42 +07:00
|
|
|
void (*msi_set_irq)(struct pcie_port *pp, int irq);
|
|
|
|
|
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
|
|
|
|
|
u32 (*get_msi_data)(struct pcie_port *pp);
|
2014-07-24 01:54:51 +07:00
|
|
|
void (*scan_bus)(struct pcie_port *pp);
|
|
|
|
|
int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
|
2013-07-31 15:14:10 +07:00
|
|
|
};
|
|
|
|
|
|
2013-12-11 16:38:32 +07:00
|
|
|
int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
|
|
|
|
|
int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
|
2014-03-28 23:52:58 +07:00
|
|
|
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
|
2013-09-06 13:54:59 +07:00
|
|
|
void dw_pcie_msi_init(struct pcie_port *pp);
|
2013-07-31 15:14:10 +07:00
|
|
|
int dw_pcie_link_up(struct pcie_port *pp);
|
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp);
|
|
|
|
|
int dw_pcie_host_init(struct pcie_port *pp);
|
2013-10-09 22:12:21 +07:00
|
|
|
|
|
|
|
|
#endif /* _PCIE_DESIGNWARE_H */
|