2019-05-27 13:55:01 +07:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2012-09-18 01:16:43 +07:00
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/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012, Samsung Electronics Co., Ltd.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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2013-08-30 22:12:50 +07:00
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#include <linux/mmc/mmc.h>
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2012-09-18 01:16:43 +07:00
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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2016-10-12 09:55:55 +07:00
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#include <linux/pm_runtime.h>
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2013-08-30 22:12:50 +07:00
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#include <linux/slab.h>
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2012-09-18 01:16:43 +07:00
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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2014-12-22 19:12:04 +07:00
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#include "dw_mmc-exynos.h"
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2013-08-30 22:13:03 +07:00
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2012-09-18 01:16:43 +07:00
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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2013-05-24 17:04:32 +07:00
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DW_MCI_TYPE_EXYNOS5420,
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2013-08-30 22:12:35 +07:00
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DW_MCI_TYPE_EXYNOS5420_SMU,
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2014-08-28 20:18:53 +07:00
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DW_MCI_TYPE_EXYNOS7,
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DW_MCI_TYPE_EXYNOS7_SMU,
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2012-09-18 01:16:43 +07:00
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};
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/* Exynos implementation specific driver private data */
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struct dw_mci_exynos_priv_data {
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enum dw_mci_exynos_type ctrl_type;
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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2015-01-29 09:41:57 +07:00
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u32 hs400_timing;
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u32 tuned_sample;
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2013-08-30 22:13:03 +07:00
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u32 cur_speed;
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2015-01-29 09:41:57 +07:00
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u32 dqs_delay;
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u32 saved_dqs_en;
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u32 saved_strobe_ctrl;
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2012-09-18 01:16:43 +07:00
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};
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static struct dw_mci_exynos_compatible {
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char *compatible;
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enum dw_mci_exynos_type ctrl_type;
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} exynos_compat[] = {
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{
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.compatible = "samsung,exynos4210-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4210,
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}, {
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.compatible = "samsung,exynos4412-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS4412,
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}, {
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.compatible = "samsung,exynos5250-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5250,
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2013-05-24 17:04:32 +07:00
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}, {
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.compatible = "samsung,exynos5420-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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2013-08-30 22:12:35 +07:00
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}, {
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.compatible = "samsung,exynos5420-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
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2014-08-28 20:18:53 +07:00
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}, {
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.compatible = "samsung,exynos7-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7,
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}, {
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.compatible = "samsung,exynos7-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
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2012-09-18 01:16:43 +07:00
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},
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};
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2015-01-29 09:41:57 +07:00
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static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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return EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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return EXYNOS4210_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
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else
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
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}
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2016-03-31 12:53:18 +07:00
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static void dw_mci_exynos_config_smu(struct dw_mci *host)
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2012-09-18 01:16:43 +07:00
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{
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2013-08-30 22:11:57 +07:00
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struct dw_mci_exynos_priv_data *priv = host->priv;
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2012-09-18 01:16:43 +07:00
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2016-03-31 12:53:18 +07:00
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/*
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* If Exynos is provided the Security management,
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* set for non-ecryption mode at this time.
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*/
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2014-08-28 20:18:53 +07:00
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
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2013-08-30 22:12:35 +07:00
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mci_writel(host, MPSBEGIN0, 0);
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2014-12-22 19:12:04 +07:00
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mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
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mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
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SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
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SDMMC_MPSCTRL_VALID |
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SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
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2013-08-30 22:12:35 +07:00
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}
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2016-03-31 12:53:18 +07:00
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}
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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dw_mci_exynos_config_smu(host);
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2013-08-30 22:12:35 +07:00
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2015-01-29 09:41:57 +07:00
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if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
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priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
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priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
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priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
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mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
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if (!priv->dqs_delay)
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priv->dqs_delay =
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DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
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}
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2014-12-22 19:12:03 +07:00
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host->bus_hz /= (priv->ciu_div + 1);
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2012-09-18 01:16:43 +07:00
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return 0;
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}
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2015-01-29 09:41:57 +07:00
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static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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2016-01-21 09:01:06 +07:00
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/*
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* Exynos4412 and Exynos5250 extends the use of CMD register with the
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* use of bit 29 (which is reserved on standard MSHC controllers) for
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* optionally bypassing the HOLD register for command and data. The
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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2017-06-05 11:41:34 +07:00
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if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot)
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set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags);
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2015-01-29 09:41:57 +07:00
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}
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2016-10-12 09:55:55 +07:00
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#ifdef CONFIG_PM
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static int dw_mci_exynos_runtime_resume(struct device *dev)
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2013-08-30 22:11:21 +07:00
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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2018-03-09 13:10:21 +07:00
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int ret;
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ret = dw_mci_runtime_resume(dev);
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if (ret)
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return ret;
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2013-08-30 22:11:21 +07:00
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2016-03-31 12:53:18 +07:00
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dw_mci_exynos_config_smu(host);
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2018-03-09 13:10:21 +07:00
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return ret;
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2013-08-30 22:11:21 +07:00
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}
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2018-06-12 17:55:23 +07:00
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#endif /* CONFIG_PM */
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#ifdef CONFIG_PM_SLEEP
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/**
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* dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
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*
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* This ensures that device will be in runtime active state in
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* dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
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*/
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static int dw_mci_exynos_suspend_noirq(struct device *dev)
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{
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pm_runtime_get_noresume(dev);
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return pm_runtime_force_suspend(dev);
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}
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2013-08-30 22:11:21 +07:00
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/**
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* dw_mci_exynos_resume_noirq - Exynos-specific resume code
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*
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* On exynos5420 there is a silicon errata that will sometimes leave the
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* WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
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* that it fired and we can clear it by writing a 1 back. Clear it to prevent
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* interrupts from going off constantly.
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*
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* We run this code on all exynos variants because it doesn't hurt.
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*/
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static int dw_mci_exynos_resume_noirq(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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2014-08-28 20:18:53 +07:00
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struct dw_mci_exynos_priv_data *priv = host->priv;
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2013-08-30 22:11:21 +07:00
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u32 clksel;
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2018-06-12 17:55:23 +07:00
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int ret;
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ret = pm_runtime_force_resume(dev);
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if (ret)
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return ret;
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2013-08-30 22:11:21 +07:00
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2014-08-28 20:18:53 +07:00
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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2013-08-30 22:11:21 +07:00
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2018-06-12 17:55:23 +07:00
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pm_runtime_put(dev);
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2013-08-30 22:11:21 +07:00
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return 0;
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}
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2018-06-12 17:55:23 +07:00
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#endif /* CONFIG_PM_SLEEP */
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2013-08-30 22:11:21 +07:00
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2015-01-29 09:41:57 +07:00
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static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
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2012-09-18 01:16:43 +07:00
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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2015-01-29 09:41:57 +07:00
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u32 dqs, strobe;
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2012-09-18 01:16:43 +07:00
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2015-01-29 09:41:57 +07:00
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/*
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* Not supported to configure register
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* related to HS400
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*/
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2016-07-14 20:22:27 +07:00
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if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) {
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if (timing == MMC_TIMING_MMC_HS400)
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dev_warn(host->dev,
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"cannot configure HS400, unsupported chipset\n");
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2015-01-29 09:41:57 +07:00
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return;
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2016-07-14 20:22:27 +07:00
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}
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2015-01-29 09:41:57 +07:00
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dqs = priv->saved_dqs_en;
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strobe = priv->saved_strobe_ctrl;
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if (timing == MMC_TIMING_MMC_HS400) {
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dqs |= DATA_STROBE_EN;
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strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
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2018-09-27 21:07:38 +07:00
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} else if (timing == MMC_TIMING_UHS_SDR104) {
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dqs &= 0xffffff00;
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2013-08-30 22:13:03 +07:00
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} else {
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2015-01-29 09:41:57 +07:00
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dqs &= ~DATA_STROBE_EN;
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2013-08-30 22:13:03 +07:00
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}
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2015-01-29 09:41:57 +07:00
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mci_writel(host, HS400_DQS_EN, dqs);
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mci_writel(host, HS400_DLINE_CTRL, strobe);
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}
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static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned long actual;
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u8 div;
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int ret;
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2014-12-22 19:12:03 +07:00
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/*
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* Don't care if wanted clock is zero or
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* ciu clock is unavailable
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*/
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if (!wanted || IS_ERR(host->ciu_clk))
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2013-08-30 22:13:03 +07:00
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return;
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/* Guaranteed minimum frequency for cclkin */
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if (wanted < EXYNOS_CCLKIN_MIN)
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wanted = EXYNOS_CCLKIN_MIN;
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2015-01-29 09:41:57 +07:00
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if (wanted == priv->cur_speed)
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return;
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div = dw_mci_exynos_get_ciu_div(host);
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ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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}
|
|
|
|
|
|
|
|
static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
|
|
unsigned int wanted = ios->clock;
|
|
|
|
u32 timing = ios->timing, clksel;
|
|
|
|
|
|
|
|
switch (timing) {
|
|
|
|
case MMC_TIMING_MMC_HS400:
|
|
|
|
/* Update tuned sample timing */
|
|
|
|
clksel = SDMMC_CLKSEL_UP_SAMPLE(
|
|
|
|
priv->hs400_timing, priv->tuned_sample);
|
|
|
|
wanted <<= 1;
|
|
|
|
break;
|
|
|
|
case MMC_TIMING_MMC_DDR52:
|
|
|
|
clksel = priv->ddr_timing;
|
|
|
|
/* Should be double rate for DDR mode */
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_8)
|
|
|
|
wanted <<= 1;
|
|
|
|
break;
|
2018-09-27 21:07:38 +07:00
|
|
|
case MMC_TIMING_UHS_SDR104:
|
|
|
|
case MMC_TIMING_UHS_SDR50:
|
|
|
|
clksel = (priv->sdr_timing & 0xfff8ffff) |
|
|
|
|
(priv->ciu_div << 16);
|
|
|
|
break;
|
|
|
|
case MMC_TIMING_UHS_DDR50:
|
|
|
|
clksel = (priv->ddr_timing & 0xfff8ffff) |
|
|
|
|
(priv->ciu_div << 16);
|
|
|
|
break;
|
2015-01-29 09:41:57 +07:00
|
|
|
default:
|
|
|
|
clksel = priv->sdr_timing;
|
2013-08-30 22:13:03 +07:00
|
|
|
}
|
2015-01-29 09:41:57 +07:00
|
|
|
|
|
|
|
/* Set clock timing for the requested speed mode*/
|
|
|
|
dw_mci_exynos_set_clksel_timing(host, clksel);
|
|
|
|
|
|
|
|
/* Configure setting for HS400 */
|
|
|
|
dw_mci_exynos_config_hs400(host, timing);
|
|
|
|
|
|
|
|
/* Configure clock rate */
|
|
|
|
dw_mci_exynos_adjust_clock(host, wanted);
|
2012-09-18 01:16:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dw_mci_exynos_parse_dt(struct dw_mci *host)
|
|
|
|
{
|
2013-08-30 22:11:57 +07:00
|
|
|
struct dw_mci_exynos_priv_data *priv;
|
2012-09-18 01:16:43 +07:00
|
|
|
struct device_node *np = host->dev->of_node;
|
|
|
|
u32 timing[2];
|
|
|
|
u32 div = 0;
|
2013-08-30 22:11:57 +07:00
|
|
|
int idx;
|
2012-09-18 01:16:43 +07:00
|
|
|
int ret;
|
|
|
|
|
2013-08-30 22:11:57 +07:00
|
|
|
priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
|
2014-12-23 19:07:33 +07:00
|
|
|
if (!priv)
|
2013-08-30 22:11:57 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
|
|
|
|
if (of_device_is_compatible(np, exynos_compat[idx].compatible))
|
|
|
|
priv->ctrl_type = exynos_compat[idx].ctrl_type;
|
|
|
|
}
|
|
|
|
|
2013-08-30 22:13:03 +07:00
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
|
|
|
|
priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
|
|
|
|
else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
|
|
|
|
priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
|
|
|
|
else {
|
|
|
|
of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
|
|
|
|
priv->ciu_div = div;
|
|
|
|
}
|
2012-09-18 01:16:43 +07:00
|
|
|
|
|
|
|
ret = of_property_read_u32_array(np,
|
|
|
|
"samsung,dw-mshc-sdr-timing", timing, 2);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-10-22 16:11:56 +07:00
|
|
|
priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
|
|
|
|
|
2012-09-18 01:16:43 +07:00
|
|
|
ret = of_property_read_u32_array(np,
|
|
|
|
"samsung,dw-mshc-ddr-timing", timing, 2);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
|
2015-01-29 09:41:57 +07:00
|
|
|
|
|
|
|
ret = of_property_read_u32_array(np,
|
|
|
|
"samsung,dw-mshc-hs400-timing", timing, 2);
|
|
|
|
if (!ret && of_property_read_u32(np,
|
|
|
|
"samsung,read-strobe-delay", &priv->dqs_delay))
|
|
|
|
dev_dbg(host->dev,
|
|
|
|
"read-strobe-delay is not found, assuming usage of default value\n");
|
|
|
|
|
|
|
|
priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
|
|
|
|
HS400_FIXED_CIU_CLK_DIV);
|
2013-08-30 22:11:57 +07:00
|
|
|
host->priv = priv;
|
2012-09-18 01:16:43 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-08-30 22:12:50 +07:00
|
|
|
static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
|
|
|
|
{
|
2014-08-28 20:18:53 +07:00
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
|
|
|
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
|
|
|
|
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
|
|
|
|
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
|
|
|
|
else
|
|
|
|
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
|
2013-08-30 22:12:50 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
|
|
|
|
{
|
|
|
|
u32 clksel;
|
2014-08-28 20:18:53 +07:00
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
|
|
|
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
|
|
|
|
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
|
|
|
|
clksel = mci_readl(host, CLKSEL64);
|
|
|
|
else
|
|
|
|
clksel = mci_readl(host, CLKSEL);
|
2015-01-29 09:41:57 +07:00
|
|
|
clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
|
2014-08-28 20:18:53 +07:00
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
|
|
|
|
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
|
|
|
|
mci_writel(host, CLKSEL64, clksel);
|
|
|
|
else
|
|
|
|
mci_writel(host, CLKSEL, clksel);
|
2013-08-30 22:12:50 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
|
|
|
|
{
|
2014-08-28 20:18:53 +07:00
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
2013-08-30 22:12:50 +07:00
|
|
|
u32 clksel;
|
|
|
|
u8 sample;
|
|
|
|
|
2014-08-28 20:18:53 +07:00
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
|
|
|
|
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
|
|
|
|
clksel = mci_readl(host, CLKSEL64);
|
|
|
|
else
|
|
|
|
clksel = mci_readl(host, CLKSEL);
|
2015-01-29 09:41:57 +07:00
|
|
|
|
2013-08-30 22:12:50 +07:00
|
|
|
sample = (clksel + 1) & 0x7;
|
2015-01-29 09:41:57 +07:00
|
|
|
clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
|
|
|
|
|
2014-08-28 20:18:53 +07:00
|
|
|
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
|
|
|
|
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
|
|
|
|
mci_writel(host, CLKSEL64, clksel);
|
|
|
|
else
|
|
|
|
mci_writel(host, CLKSEL, clksel);
|
2015-01-29 09:41:57 +07:00
|
|
|
|
2013-08-30 22:12:50 +07:00
|
|
|
return sample;
|
|
|
|
}
|
|
|
|
|
|
|
|
static s8 dw_mci_exynos_get_best_clksmpl(u8 candiates)
|
|
|
|
{
|
|
|
|
const u8 iter = 8;
|
|
|
|
u8 __c;
|
|
|
|
s8 i, loc = -1;
|
|
|
|
|
|
|
|
for (i = 0; i < iter; i++) {
|
|
|
|
__c = ror8(candiates, i);
|
|
|
|
if ((__c & 0xc7) == 0xc7) {
|
|
|
|
loc = i;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < iter; i++) {
|
|
|
|
__c = ror8(candiates, i);
|
|
|
|
if ((__c & 0x83) == 0x83) {
|
|
|
|
loc = i;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return loc;
|
|
|
|
}
|
|
|
|
|
2015-10-27 13:24:28 +07:00
|
|
|
static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
|
2013-08-30 22:12:50 +07:00
|
|
|
{
|
|
|
|
struct dw_mci *host = slot->host;
|
2015-01-29 09:41:57 +07:00
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
2013-08-30 22:12:50 +07:00
|
|
|
struct mmc_host *mmc = slot->mmc;
|
|
|
|
u8 start_smpl, smpl, candiates = 0;
|
|
|
|
s8 found = -1;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
start_smpl = dw_mci_exynos_get_clksmpl(host);
|
|
|
|
|
|
|
|
do {
|
|
|
|
mci_writel(host, TMOUT, ~0);
|
|
|
|
smpl = dw_mci_exynos_move_next_clksmpl(host);
|
|
|
|
|
2015-10-27 13:24:28 +07:00
|
|
|
if (!mmc_send_tuning(mmc, opcode, NULL))
|
2014-12-01 22:13:39 +07:00
|
|
|
candiates |= (1 << smpl);
|
2013-08-30 22:12:50 +07:00
|
|
|
|
|
|
|
} while (start_smpl != smpl);
|
|
|
|
|
|
|
|
found = dw_mci_exynos_get_best_clksmpl(candiates);
|
2015-01-29 09:41:57 +07:00
|
|
|
if (found >= 0) {
|
2013-08-30 22:12:50 +07:00
|
|
|
dw_mci_exynos_set_clksmpl(host, found);
|
2015-01-29 09:41:57 +07:00
|
|
|
priv->tuned_sample = found;
|
|
|
|
} else {
|
2013-08-30 22:12:50 +07:00
|
|
|
ret = -EIO;
|
2015-01-29 09:41:57 +07:00
|
|
|
}
|
2013-08-30 22:12:50 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-05 17:02:54 +07:00
|
|
|
static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
|
2015-01-29 09:41:57 +07:00
|
|
|
struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct dw_mci_exynos_priv_data *priv = host->priv;
|
|
|
|
|
|
|
|
dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
|
|
|
|
dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-22 22:17:45 +07:00
|
|
|
/* Common capabilities of Exynos4/Exynos5 SoC */
|
|
|
|
static unsigned long exynos_dwmmc_caps[4] = {
|
2014-03-14 19:12:43 +07:00
|
|
|
MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
|
2012-09-18 01:16:43 +07:00
|
|
|
MMC_CAP_CMD23,
|
|
|
|
MMC_CAP_CMD23,
|
|
|
|
MMC_CAP_CMD23,
|
|
|
|
};
|
|
|
|
|
2013-02-22 22:17:45 +07:00
|
|
|
static const struct dw_mci_drv_data exynos_drv_data = {
|
|
|
|
.caps = exynos_dwmmc_caps,
|
2018-02-24 13:17:23 +07:00
|
|
|
.num_caps = ARRAY_SIZE(exynos_dwmmc_caps),
|
2012-09-18 01:16:43 +07:00
|
|
|
.init = dw_mci_exynos_priv_init,
|
|
|
|
.set_ios = dw_mci_exynos_set_ios,
|
|
|
|
.parse_dt = dw_mci_exynos_parse_dt,
|
2013-08-30 22:12:50 +07:00
|
|
|
.execute_tuning = dw_mci_exynos_execute_tuning,
|
2015-01-29 09:41:57 +07:00
|
|
|
.prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
|
2012-09-18 01:16:43 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id dw_mci_exynos_match[] = {
|
2013-02-22 22:17:45 +07:00
|
|
|
{ .compatible = "samsung,exynos4412-dw-mshc",
|
|
|
|
.data = &exynos_drv_data, },
|
2012-09-18 01:16:43 +07:00
|
|
|
{ .compatible = "samsung,exynos5250-dw-mshc",
|
2013-02-22 22:17:45 +07:00
|
|
|
.data = &exynos_drv_data, },
|
2013-05-24 17:04:32 +07:00
|
|
|
{ .compatible = "samsung,exynos5420-dw-mshc",
|
|
|
|
.data = &exynos_drv_data, },
|
2013-08-30 22:12:35 +07:00
|
|
|
{ .compatible = "samsung,exynos5420-dw-mshc-smu",
|
|
|
|
.data = &exynos_drv_data, },
|
2014-08-28 20:18:53 +07:00
|
|
|
{ .compatible = "samsung,exynos7-dw-mshc",
|
|
|
|
.data = &exynos_drv_data, },
|
|
|
|
{ .compatible = "samsung,exynos7-dw-mshc-smu",
|
|
|
|
.data = &exynos_drv_data, },
|
2012-09-18 01:16:43 +07:00
|
|
|
{},
|
|
|
|
};
|
2012-11-07 04:55:30 +07:00
|
|
|
MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
|
2012-09-18 01:16:43 +07:00
|
|
|
|
2013-02-18 15:53:08 +07:00
|
|
|
static int dw_mci_exynos_probe(struct platform_device *pdev)
|
2012-09-18 01:16:43 +07:00
|
|
|
{
|
2012-11-07 04:55:31 +07:00
|
|
|
const struct dw_mci_drv_data *drv_data;
|
2012-09-18 01:16:43 +07:00
|
|
|
const struct of_device_id *match;
|
2016-11-23 16:36:02 +07:00
|
|
|
int ret;
|
2012-09-18 01:16:43 +07:00
|
|
|
|
|
|
|
match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
|
|
|
|
drv_data = match->data;
|
2016-11-23 16:36:02 +07:00
|
|
|
|
|
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
|
|
ret = dw_mci_pltfm_register(pdev, drv_data);
|
|
|
|
if (ret) {
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dw_mci_exynos_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
|
|
|
|
return dw_mci_pltfm_remove(pdev);
|
2012-09-18 01:16:43 +07:00
|
|
|
}
|
|
|
|
|
2014-03-04 12:03:25 +07:00
|
|
|
static const struct dev_pm_ops dw_mci_exynos_pmops = {
|
2018-06-12 17:55:23 +07:00
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq,
|
|
|
|
dw_mci_exynos_resume_noirq)
|
2016-10-12 09:55:55 +07:00
|
|
|
SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
|
|
|
|
dw_mci_exynos_runtime_resume,
|
|
|
|
NULL)
|
2013-08-30 22:11:21 +07:00
|
|
|
};
|
|
|
|
|
2012-09-18 01:16:43 +07:00
|
|
|
static struct platform_driver dw_mci_exynos_pltfm_driver = {
|
|
|
|
.probe = dw_mci_exynos_probe,
|
2016-11-23 16:36:02 +07:00
|
|
|
.remove = dw_mci_exynos_remove,
|
2012-09-18 01:16:43 +07:00
|
|
|
.driver = {
|
|
|
|
.name = "dwmmc_exynos",
|
2013-02-18 15:53:09 +07:00
|
|
|
.of_match_table = dw_mci_exynos_match,
|
2013-08-30 22:11:21 +07:00
|
|
|
.pm = &dw_mci_exynos_pmops,
|
2012-09-18 01:16:43 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(dw_mci_exynos_pltfm_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
|
|
|
|
MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
2015-05-14 15:59:45 +07:00
|
|
|
MODULE_ALIAS("platform:dwmmc_exynos");
|