2019-11-19 22:47:23 +07:00
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "intel_context.h"
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#include "intel_engine_pm.h"
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#include "intel_gt_requests.h"
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#include "intel_ring.h"
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#include "selftest_rc6.h"
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#include "selftests/i915_random.h"
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2019-11-27 16:56:57 +07:00
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int live_rc6_manual(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_rc6 *rc6 = >->rc6;
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intel_wakeref_t wakeref;
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u64 res[2];
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int err = 0;
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/*
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* Our claim is that we can "encourage" the GPU to enter rc6 at will.
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* Let's try it!
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*/
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if (!rc6->enabled)
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return 0;
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/* bsw/byt use a PCU and decouple RC6 from our manual control */
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if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
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return 0;
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wakeref = intel_runtime_pm_get(gt->uncore->rpm);
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/* Force RC6 off for starters */
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__intel_rc6_disable(rc6);
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msleep(1); /* wakeup is not immediate, takes about 100us on icl */
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res[0] = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
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msleep(250);
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res[1] = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
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if ((res[1] - res[0]) >> 10) {
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pr_err("RC6 residency increased by %lldus while disabled for 250ms!\n",
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(res[1] - res[0]) >> 10);
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err = -EINVAL;
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goto out_unlock;
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}
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/* Manually enter RC6 */
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intel_rc6_park(rc6);
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res[0] = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
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msleep(100);
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res[1] = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
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if (res[1] == res[0]) {
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2020-01-23 21:57:55 +07:00
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pr_err("Did not enter RC6! RC6_STATE=%08x, RC6_CONTROL=%08x, residency=%lld\n",
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2019-11-27 16:56:57 +07:00
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intel_uncore_read_fw(gt->uncore, GEN6_RC_STATE),
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2020-01-23 21:57:55 +07:00
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intel_uncore_read_fw(gt->uncore, GEN6_RC_CONTROL),
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res[0]);
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2019-11-27 16:56:57 +07:00
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err = -EINVAL;
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}
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/* Restore what should have been the original state! */
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intel_rc6_unpark(rc6);
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out_unlock:
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intel_runtime_pm_put(gt->uncore->rpm, wakeref);
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return err;
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}
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2019-11-19 22:47:23 +07:00
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static const u32 *__live_rc6_ctx(struct intel_context *ce)
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{
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struct i915_request *rq;
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const u32 *result;
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u32 cmd;
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u32 *cs;
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return ERR_CAST(rq);
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs)) {
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i915_request_add(rq);
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return cs;
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}
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cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
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if (INTEL_GEN(rq->i915) >= 8)
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cmd++;
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*cs++ = cmd;
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*cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);
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*cs++ = ce->timeline->hwsp_offset + 8;
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*cs++ = 0;
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intel_ring_advance(rq, cs);
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result = rq->hwsp_seqno + 2;
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i915_request_add(rq);
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return result;
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}
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static struct intel_engine_cs **
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randomised_engines(struct intel_gt *gt,
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struct rnd_state *prng,
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unsigned int *count)
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{
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struct intel_engine_cs *engine, **engines;
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enum intel_engine_id id;
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int n;
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n = 0;
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for_each_engine(engine, gt, id)
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n++;
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if (!n)
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return NULL;
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engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
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if (!engines)
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return NULL;
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n = 0;
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for_each_engine(engine, gt, id)
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engines[n++] = engine;
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i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
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*count = n;
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return engines;
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}
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int live_rc6_ctx_wa(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs **engines;
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unsigned int n, count;
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I915_RND_STATE(prng);
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int err = 0;
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/* A read of CTX_INFO upsets rc6. Poke the bear! */
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if (INTEL_GEN(gt->i915) < 8)
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return 0;
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engines = randomised_engines(gt, &prng, &count);
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if (!engines)
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return 0;
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for (n = 0; n < count; n++) {
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struct intel_engine_cs *engine = engines[n];
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int pass;
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for (pass = 0; pass < 2; pass++) {
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struct intel_context *ce;
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unsigned int resets =
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i915_reset_engine_count(>->i915->gpu_error,
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engine);
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const u32 *res;
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/* Use a sacrifical context */
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2019-12-21 23:03:24 +07:00
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ce = intel_context_create(engine);
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2019-11-19 22:47:23 +07:00
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto out;
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}
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intel_engine_pm_get(engine);
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res = __live_rc6_ctx(ce);
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intel_engine_pm_put(engine);
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intel_context_put(ce);
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if (IS_ERR(res)) {
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err = PTR_ERR(res);
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goto out;
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}
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if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
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intel_gt_set_wedged(gt);
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err = -ETIME;
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goto out;
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}
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intel_gt_pm_wait_for_idle(gt);
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pr_debug("%s: CTX_INFO=%0x\n",
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engine->name, READ_ONCE(*res));
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if (resets !=
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i915_reset_engine_count(>->i915->gpu_error,
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engine)) {
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pr_err("%s: GPU reset required\n",
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engine->name);
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add_taint_for_CI(TAINT_WARN);
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err = -EIO;
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goto out;
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}
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}
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}
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out:
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kfree(engines);
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return err;
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}
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