2019-06-04 15:11:33 +07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
2008-10-31 20:08:02 +07:00
|
|
|
/*
|
|
|
|
* linux/arch/arm/mm/copypage-v4wt.S
|
|
|
|
*
|
|
|
|
* Copyright (C) 1995-1999 Russell King
|
|
|
|
*
|
|
|
|
* This is for CPUs with a writethrough cache and 'flush ID cache' is
|
|
|
|
* the only supported cache operation.
|
|
|
|
*/
|
|
|
|
#include <linux/init.h>
|
2008-10-31 22:08:35 +07:00
|
|
|
#include <linux/highmem.h>
|
2008-10-31 20:08:02 +07:00
|
|
|
|
|
|
|
/*
|
2008-10-31 22:08:35 +07:00
|
|
|
* ARMv4 optimised copy_user_highpage
|
2008-10-31 20:08:02 +07:00
|
|
|
*
|
|
|
|
* Since we have writethrough caches, we don't have to worry about
|
|
|
|
* dirty data in the cache. However, we do have to ensure that
|
|
|
|
* subsequent reads are up to date.
|
|
|
|
*/
|
2018-11-07 23:49:00 +07:00
|
|
|
static void v4wt_copy_user_page(void *kto, const void *kfrom)
|
2008-10-31 20:08:02 +07:00
|
|
|
{
|
2018-11-07 23:49:00 +07:00
|
|
|
int tmp;
|
|
|
|
|
|
|
|
asm volatile ("\
|
2019-02-18 06:58:29 +07:00
|
|
|
.syntax unified\n\
|
2018-11-07 23:49:00 +07:00
|
|
|
ldmia %1!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
1: stmia %0!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\
|
|
|
|
stmia %0!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
ldmia %1!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
stmia %0!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
ldmia %1!, {r3, r4, ip, lr} @ 4\n\
|
|
|
|
subs %2, %2, #1 @ 1\n\
|
|
|
|
stmia %0!, {r3, r4, ip, lr} @ 4\n\
|
2019-02-18 06:58:29 +07:00
|
|
|
ldmiane %1!, {r3, r4, ip, lr} @ 4\n\
|
2008-10-31 20:08:02 +07:00
|
|
|
bne 1b @ 1\n\
|
2018-11-07 23:49:00 +07:00
|
|
|
mcr p15, 0, %2, c7, c7, 0 @ flush ID cache"
|
|
|
|
: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
|
|
|
|
: "2" (PAGE_SIZE / 64)
|
|
|
|
: "r3", "r4", "ip", "lr");
|
2008-10-31 20:08:02 +07:00
|
|
|
}
|
|
|
|
|
2008-10-31 22:08:35 +07:00
|
|
|
void v4wt_copy_user_highpage(struct page *to, struct page *from,
|
2009-10-05 21:17:45 +07:00
|
|
|
unsigned long vaddr, struct vm_area_struct *vma)
|
2008-10-31 22:08:35 +07:00
|
|
|
{
|
|
|
|
void *kto, *kfrom;
|
|
|
|
|
2011-11-25 22:14:15 +07:00
|
|
|
kto = kmap_atomic(to);
|
|
|
|
kfrom = kmap_atomic(from);
|
2008-10-31 22:08:35 +07:00
|
|
|
v4wt_copy_user_page(kto, kfrom);
|
2011-11-25 22:14:15 +07:00
|
|
|
kunmap_atomic(kfrom);
|
|
|
|
kunmap_atomic(kto);
|
2008-10-31 22:08:35 +07:00
|
|
|
}
|
|
|
|
|
2008-10-31 20:08:02 +07:00
|
|
|
/*
|
|
|
|
* ARMv4 optimised clear_user_page
|
|
|
|
*
|
|
|
|
* Same story as above.
|
|
|
|
*/
|
2008-10-31 23:32:19 +07:00
|
|
|
void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
|
2008-10-31 20:08:02 +07:00
|
|
|
{
|
2011-11-25 22:14:15 +07:00
|
|
|
void *ptr, *kaddr = kmap_atomic(page);
|
2008-11-04 14:42:27 +07:00
|
|
|
asm volatile("\
|
|
|
|
mov r1, %2 @ 1\n\
|
2008-10-31 20:08:02 +07:00
|
|
|
mov r2, #0 @ 1\n\
|
|
|
|
mov r3, #0 @ 1\n\
|
|
|
|
mov ip, #0 @ 1\n\
|
|
|
|
mov lr, #0 @ 1\n\
|
2008-10-31 23:32:19 +07:00
|
|
|
1: stmia %0!, {r2, r3, ip, lr} @ 4\n\
|
|
|
|
stmia %0!, {r2, r3, ip, lr} @ 4\n\
|
|
|
|
stmia %0!, {r2, r3, ip, lr} @ 4\n\
|
|
|
|
stmia %0!, {r2, r3, ip, lr} @ 4\n\
|
2008-10-31 20:08:02 +07:00
|
|
|
subs r1, r1, #1 @ 1\n\
|
|
|
|
bne 1b @ 1\n\
|
2008-10-31 23:32:19 +07:00
|
|
|
mcr p15, 0, r2, c7, c7, 0 @ flush ID cache"
|
2008-11-04 14:42:27 +07:00
|
|
|
: "=r" (ptr)
|
|
|
|
: "0" (kaddr), "I" (PAGE_SIZE / 64)
|
2008-10-31 23:32:19 +07:00
|
|
|
: "r1", "r2", "r3", "ip", "lr");
|
2011-11-25 22:14:15 +07:00
|
|
|
kunmap_atomic(kaddr);
|
2008-10-31 20:08:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
struct cpu_user_fns v4wt_user_fns __initdata = {
|
2008-10-31 23:32:19 +07:00
|
|
|
.cpu_clear_user_highpage = v4wt_clear_user_highpage,
|
2008-10-31 22:08:35 +07:00
|
|
|
.cpu_copy_user_highpage = v4wt_copy_user_highpage,
|
2008-10-31 20:08:02 +07:00
|
|
|
};
|