linux_dsm_epyc7002/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi

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// SPDX-License-Identifier: GPL-2.0
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
/*
* Device tree sources for Exynos5433 thermal zone
*
* Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
*/
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
atlas0_thermal: atlas0-thermal {
thermal-sensors = <&tmu_atlas0>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
atlas0_alert_0: atlas0-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_1: atlas0-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_2: atlas0-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_3: atlas0-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_4: atlas0-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_5: atlas0-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas0_alert_6: atlas0-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map0 {
/* Set maximum frequency as 1800MHz */
trip = <&atlas0_alert_0>;
cooling-device = <&cpu4 1 2>, <&cpu5 1 2>,
<&cpu6 1 2>, <&cpu7 1 2>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map1 {
/* Set maximum frequency as 1700MHz */
trip = <&atlas0_alert_1>;
cooling-device = <&cpu4 2 3>, <&cpu5 2 3>,
<&cpu6 2 3>, <&cpu7 2 3>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map2 {
/* Set maximum frequency as 1600MHz */
trip = <&atlas0_alert_2>;
cooling-device = <&cpu4 3 4>, <&cpu5 3 4>,
<&cpu6 3 4>, <&cpu7 3 4>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map3 {
/* Set maximum frequency as 1500MHz */
trip = <&atlas0_alert_3>;
cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
<&cpu6 4 5>, <&cpu7 4 5>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map4 {
/* Set maximum frequency as 1400MHz */
trip = <&atlas0_alert_4>;
cooling-device = <&cpu4 5 7>, <&cpu5 5 7>,
<&cpu6 5 7>, <&cpu7 5 7>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map5 {
/* Set maximum frequencyas 1200MHz */
trip = <&atlas0_alert_5>;
cooling-device = <&cpu4 7 9>, <&cpu5 7 9>,
<&cpu6 7 9>, <&cpu7 7 9>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map6 {
/* Set maximum frequency as 1000MHz */
trip = <&atlas0_alert_6>;
cooling-device = <&cpu4 9 14>, <&cpu5 9 14>,
<&cpu6 9 14>, <&cpu7 9 14>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
};
};
atlas1_thermal: atlas1-thermal {
thermal-sensors = <&tmu_atlas1>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
atlas1_alert_0: atlas1-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_1: atlas1-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_2: atlas1-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_3: atlas1-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_4: atlas1-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_5: atlas1-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
atlas1_alert_6: atlas1-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
g3d_thermal: g3d-thermal {
thermal-sensors = <&tmu_g3d>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
g3d_alert_0: g3d-alert-0 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_1: g3d-alert-1 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_2: g3d-alert-2 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_3: g3d-alert-3 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_4: g3d-alert-4 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_5: g3d-alert-5 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
g3d_alert_6: g3d-alert-6 {
temperature = <100000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
apollo_thermal: apollo-thermal {
thermal-sensors = <&tmu_apollo>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
apollo_alert_0: apollo-alert-0 {
temperature = <65000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_1: apollo-alert-1 {
temperature = <70000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_2: apollo-alert-2 {
temperature = <75000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_3: apollo-alert-3 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_4: apollo-alert-4 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_5: apollo-alert-5 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
apollo_alert_6: apollo-alert-6 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
map0 {
/* Set maximum frequency as 1200MHz */
trip = <&apollo_alert_2>;
cooling-device = <&cpu0 1 2>, <&cpu1 1 2>,
<&cpu2 1 2>, <&cpu3 1 2>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map1 {
/* Set maximum frequency as 1100MHz */
trip = <&apollo_alert_3>;
cooling-device = <&cpu0 2 3>, <&cpu1 2 3>,
<&cpu2 2 3>, <&cpu3 2 3>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map2 {
/* Set maximum frequency as 1000MHz */
trip = <&apollo_alert_4>;
cooling-device = <&cpu0 3 4>, <&cpu1 3 4>,
<&cpu2 3 4>, <&cpu3 3 4>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map3 {
/* Set maximum frequency as 900MHz */
trip = <&apollo_alert_5>;
cooling-device = <&cpu0 4 5>, <&cpu1 4 5>,
<&cpu2 4 5>, <&cpu3 4 5>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
map4 {
/* Set maximum frequency as 800MHz */
trip = <&apollo_alert_6>;
cooling-device = <&cpu0 5 9>, <&cpu1 5 9>,
<&cpu2 5 9>, <&cpu3 5 9>;
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). Exynos5433 supports PSCI (Power State Coordination Interface) v0.1. This patch includes following Device Tree nodes to support Exynos5433 SoC: 1. Octa cores for big.LITTLE architecture - Cortex-A53 LITTLE Quad-core - Cortex-A57 big Quad-core - Supporting PSCI v0.1 2. Clock controller nodes - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS - CMU_CPIF : clocks for LLI (Low Latency Interface) - CMU_MIF : clocks for DRAM Memory Controller - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA - CMU_G2D : clocks for G2D/MDMA - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses - CMU_G3D : clocks for 3D Graphics Engine - CMU_GSCL : clocks for GSCALER - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor. - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor, CoreSight and L2 cache controller. - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs. - CMU_MFC : clocks for MFC (Multi-Format Codec) IP. - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP. - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs. 3. Pinctrl nodes for GPIO - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad 4. Timers - ARM architecture timer (armv8-timer) - MCT (Multi Core Timer) timer 5. Interrupt controller (GIC-400) 6. BUS devices - HS-I2C (High-Speed I2C) device - SPI (Serial Peripheral Interface) device 7. Sound devices - I2S bus - LPASS (Low Power Audio Subsystem) 8. Power management devices - CPUFREQ for for Cortex-A53/A57 - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP 9. Display controller devices - DECON (Display and enhancement controller) for panel output - DSI (Display Serial Interface) - MIC (Mobile Image Compressor) 10. USB - USB 3.0 DRD (Dual Role Device) controller - USB 3.0 Host controller 11. Storage devices - MSHC (Mobile Storage Host Controller) 12. Misc devices - UART devices - ADC (Analog Digital Converter) - PWM (Pulse Width Modulation) - ADMA (Advanced DMA) and PDMA (Peripheral DMA) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Ingi kim <ingi2.kim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2016-11-03 13:39:07 +07:00
};
};
};
isp_thermal: isp-thermal {
thermal-sensors = <&tmu_isp>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
isp_alert_0: isp-alert-0 {
temperature = <80000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_1: isp-alert-1 {
temperature = <85000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_2: isp-alert-2 {
temperature = <90000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_3: isp-alert-3 {
temperature = <95000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_4: isp-alert-4 {
temperature = <100000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_5: isp-alert-5 {
temperature = <105000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
isp_alert_6: isp-alert-6 {
temperature = <110000>; /* millicelsius */
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
};
};
};