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25 lines
1.1 KiB
Plaintext
25 lines
1.1 KiB
Plaintext
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What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Add/remove a sink from a trace path. There can be multiple
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source for a single sink.
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ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
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What: /sys/bus/coresight/devices/<memory_map>.etb/status
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) List various control and status registers. The specific
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layout and content is driver specific.
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What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Disables write access to the Trace RAM by stopping the
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formatter after a defined number of words have been stored
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following the trigger event. The number of 32-bit words written
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into the Trace RAM following the trigger event is equal to the
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value stored in this register+1 (from ARM ETB-TRM).
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