2005-04-17 05:20:36 +07:00
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/*
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* linux/arch/alpha/kernel/sys_titan.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996, 1999 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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* Copyright (C) 1999, 2000 Jeff Wiedemeier
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*
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* Code supporting TITAN systems (EV6+TITAN), currently:
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* Privateer
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* Falcon
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* Granite
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_titan.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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#include "err_impl.h"
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/*
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* Titan generic
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*/
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/*
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* Titan supports up to 4 CPUs
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*/
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static unsigned long titan_cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL };
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/*
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* Mask is set (1) if enabled
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*/
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static unsigned long titan_cached_irq_mask;
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/*
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* Need SMP-safe access to interrupt CSRs
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*/
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DEFINE_SPINLOCK(titan_irq_lock);
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static void
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titan_update_irq_hw(unsigned long mask)
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{
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register titan_cchip *cchip = TITAN_cchip;
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unsigned long isa_enable = 1UL << 55;
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register int bcpu = boot_cpuid;
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#ifdef CONFIG_SMP
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2006-06-04 16:51:34 +07:00
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cpumask_t cpm = cpu_present_map;
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2005-04-17 05:20:36 +07:00
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volatile unsigned long *dim0, *dim1, *dim2, *dim3;
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unsigned long mask0, mask1, mask2, mask3, dummy;
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mask &= ~isa_enable;
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mask0 = mask & titan_cpu_irq_affinity[0];
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mask1 = mask & titan_cpu_irq_affinity[1];
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mask2 = mask & titan_cpu_irq_affinity[2];
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mask3 = mask & titan_cpu_irq_affinity[3];
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if (bcpu == 0) mask0 |= isa_enable;
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else if (bcpu == 1) mask1 |= isa_enable;
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else if (bcpu == 2) mask2 |= isa_enable;
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else mask3 |= isa_enable;
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dim0 = &cchip->dim0.csr;
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dim1 = &cchip->dim1.csr;
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dim2 = &cchip->dim2.csr;
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dim3 = &cchip->dim3.csr;
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if (!cpu_isset(0, cpm)) dim0 = &dummy;
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if (!cpu_isset(1, cpm)) dim1 = &dummy;
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if (!cpu_isset(2, cpm)) dim2 = &dummy;
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if (!cpu_isset(3, cpm)) dim3 = &dummy;
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*dim0 = mask0;
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*dim1 = mask1;
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*dim2 = mask2;
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*dim3 = mask3;
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mb();
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*dim0;
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*dim1;
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*dim2;
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*dim3;
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#else
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volatile unsigned long *dimB;
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dimB = &cchip->dim0.csr;
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if (bcpu == 1) dimB = &cchip->dim1.csr;
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else if (bcpu == 2) dimB = &cchip->dim2.csr;
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else if (bcpu == 3) dimB = &cchip->dim3.csr;
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*dimB = mask | isa_enable;
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mb();
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*dimB;
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#endif
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}
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static inline void
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titan_enable_irq(unsigned int irq)
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{
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spin_lock(&titan_irq_lock);
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titan_cached_irq_mask |= 1UL << (irq - 16);
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titan_update_irq_hw(titan_cached_irq_mask);
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spin_unlock(&titan_irq_lock);
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}
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static inline void
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titan_disable_irq(unsigned int irq)
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{
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spin_lock(&titan_irq_lock);
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titan_cached_irq_mask &= ~(1UL << (irq - 16));
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titan_update_irq_hw(titan_cached_irq_mask);
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spin_unlock(&titan_irq_lock);
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}
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static unsigned int
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titan_startup_irq(unsigned int irq)
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{
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titan_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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titan_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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titan_enable_irq(irq);
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}
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static void
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titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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{
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int cpu;
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for (cpu = 0; cpu < 4; cpu++) {
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if (cpu_isset(cpu, affinity))
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titan_cpu_irq_affinity[cpu] |= 1UL << irq;
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else
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titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
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}
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}
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static void
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titan_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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{
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spin_lock(&titan_irq_lock);
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titan_cpu_set_irq_affinity(irq - 16, affinity);
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titan_update_irq_hw(titan_cached_irq_mask);
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spin_unlock(&titan_irq_lock);
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}
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static void
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2006-10-08 20:36:08 +07:00
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titan_device_interrupt(unsigned long vector)
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2005-04-17 05:20:36 +07:00
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{
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printk("titan_device_interrupt: NOT IMPLEMENTED YET!! \n");
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}
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static void
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2006-10-08 20:36:08 +07:00
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titan_srm_device_interrupt(unsigned long vector)
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2005-04-17 05:20:36 +07:00
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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2006-10-08 20:37:32 +07:00
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handle_irq(irq);
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2005-04-17 05:20:36 +07:00
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}
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static void __init
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init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
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{
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long i;
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for (i = imin; i <= imax; ++i) {
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irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 16:24:36 +07:00
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irq_desc[i].chip = ops;
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2005-04-17 05:20:36 +07:00
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}
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}
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static struct hw_interrupt_type titan_irq_type = {
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.typename = "TITAN",
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.startup = titan_startup_irq,
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.shutdown = titan_disable_irq,
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.enable = titan_enable_irq,
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.disable = titan_disable_irq,
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.ack = titan_disable_irq,
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.end = titan_end_irq,
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.set_affinity = titan_set_irq_affinity,
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};
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static irqreturn_t
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2006-10-09 18:46:52 +07:00
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titan_intr_nop(int irq, void *dev_id)
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2005-04-17 05:20:36 +07:00
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{
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/*
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* This is a NOP interrupt handler for the purposes of
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* event counting -- just return.
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*/
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return IRQ_HANDLED;
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}
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static void __init
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titan_init_irq(void)
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{
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if (alpha_using_srm && !alpha_mv.device_interrupt)
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alpha_mv.device_interrupt = titan_srm_device_interrupt;
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if (!alpha_mv.device_interrupt)
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alpha_mv.device_interrupt = titan_device_interrupt;
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titan_update_irq_hw(0);
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init_titan_irqs(&titan_irq_type, 16, 63 + 16);
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}
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static void __init
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titan_legacy_init_irq(void)
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{
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/* init the legacy dma controller */
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outb(0, DMA1_RESET_REG);
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outb(0, DMA2_RESET_REG);
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
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outb(0, DMA2_MASK_REG);
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/* init the legacy irq controller */
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init_i8259a_irqs();
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/* init the titan irqs */
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titan_init_irq();
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}
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void
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2006-10-08 20:45:28 +07:00
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titan_dispatch_irqs(u64 mask)
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2005-04-17 05:20:36 +07:00
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{
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unsigned long vector;
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/*
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* Mask down to those interrupts which are enable on this processor
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*/
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mask &= titan_cpu_irq_affinity[smp_processor_id()];
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/*
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* Dispatch all requested interrupts
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*/
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while (mask) {
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/* convert to SRM vector... priority is <63> -> <0> */
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__asm__("ctlz %1, %0" : "=r"(vector) : "r"(mask));
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vector = 63 - vector;
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mask &= ~(1UL << vector); /* clear it out */
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vector = 0x900 + (vector << 4); /* convert to SRM vector */
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/* dispatch it */
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2006-10-08 20:36:08 +07:00
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alpha_mv.device_interrupt(vector);
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2005-04-17 05:20:36 +07:00
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}
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}
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/*
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* Titan Family
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*/
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static void __init
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titan_late_init(void)
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{
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/*
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* Enable the system error interrupts. These interrupts are
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* all reported to the kernel as machine checks, so the handler
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* is a nop so it can be called to count the individual events.
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*/
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2006-07-02 09:29:11 +07:00
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request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
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2005-04-17 05:20:36 +07:00
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"CChip Error", NULL);
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2006-07-02 09:29:11 +07:00
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request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
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2005-04-17 05:20:36 +07:00
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"PChip 0 H_Error", NULL);
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2006-07-02 09:29:11 +07:00
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request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
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2005-04-17 05:20:36 +07:00
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"PChip 1 H_Error", NULL);
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2006-07-02 09:29:11 +07:00
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request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
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2005-04-17 05:20:36 +07:00
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"PChip 0 C_Error", NULL);
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2006-07-02 09:29:11 +07:00
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request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
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2005-04-17 05:20:36 +07:00
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"PChip 1 C_Error", NULL);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Register our error handlers.
|
|
|
|
|
*/
|
|
|
|
|
titan_register_error_handlers();
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check if the console left us any error logs.
|
|
|
|
|
*/
|
|
|
|
|
cdl_check_console_data_log();
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __devinit
|
|
|
|
|
titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|
|
|
|
{
|
|
|
|
|
u8 intline;
|
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
|
|
/* Get the current intline. */
|
|
|
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
|
|
|
|
|
irq = intline;
|
|
|
|
|
|
|
|
|
|
/* Is it explicitly routed through ISA? */
|
|
|
|
|
if ((irq & 0xF0) == 0xE0)
|
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
|
|
/* Offset by 16 to make room for ISA interrupts 0 - 15. */
|
|
|
|
|
return irq + 16;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
titan_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* This isn't really the right place, but there's some init
|
|
|
|
|
* that needs to be done after everything is basically up.
|
|
|
|
|
*/
|
|
|
|
|
titan_late_init();
|
|
|
|
|
|
|
|
|
|
pci_probe_only = 1;
|
|
|
|
|
common_init_pci();
|
|
|
|
|
SMC669_Init(0);
|
|
|
|
|
#ifdef CONFIG_VGA_HOSE
|
|
|
|
|
locate_and_init_vga(NULL);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Privateer
|
|
|
|
|
*/
|
|
|
|
|
static void __init
|
|
|
|
|
privateer_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* Hook a couple of extra err interrupts that the
|
|
|
|
|
* common titan code won't.
|
|
|
|
|
*/
|
2006-07-02 09:29:11 +07:00
|
|
|
|
request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
|
2005-04-17 05:20:36 +07:00
|
|
|
|
"NMI", NULL);
|
2006-07-02 09:29:11 +07:00
|
|
|
|
request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
|
2005-04-17 05:20:36 +07:00
|
|
|
|
"Temperature Warning", NULL);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Finish with the common version.
|
|
|
|
|
*/
|
|
|
|
|
return titan_init_pci();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vectors.
|
|
|
|
|
*/
|
|
|
|
|
struct alpha_machine_vector titan_mv __initmv = {
|
|
|
|
|
.vector_name = "TITAN",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TITAN_IO,
|
|
|
|
|
.machine_check = titan_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TITAN_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 80, /* 64 + 16 */
|
|
|
|
|
/* device_interrupt will be filled in by titan_init_irq */
|
|
|
|
|
|
|
|
|
|
.agp_info = titan_agp_info,
|
|
|
|
|
|
|
|
|
|
.init_arch = titan_init_arch,
|
|
|
|
|
.init_irq = titan_legacy_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = titan_init_pci,
|
|
|
|
|
|
|
|
|
|
.kill_arch = titan_kill_arch,
|
|
|
|
|
.pci_map_irq = titan_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(titan)
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector privateer_mv __initmv = {
|
|
|
|
|
.vector_name = "PRIVATEER",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TITAN_IO,
|
|
|
|
|
.machine_check = privateer_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TITAN_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 80, /* 64 + 16 */
|
|
|
|
|
/* device_interrupt will be filled in by titan_init_irq */
|
|
|
|
|
|
|
|
|
|
.agp_info = titan_agp_info,
|
|
|
|
|
|
|
|
|
|
.init_arch = titan_init_arch,
|
|
|
|
|
.init_irq = titan_legacy_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = privateer_init_pci,
|
|
|
|
|
|
|
|
|
|
.kill_arch = titan_kill_arch,
|
|
|
|
|
.pci_map_irq = titan_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
/* No alpha_mv alias for privateer since we compile it
|
|
|
|
|
in unconditionally with titan; setup_arch knows how to cope. */
|